Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1831

8

0b

RO

This status indicates a write transfer is active. 

If this bit is 0, it means no valid write data exists in the Host Controller. Refer to Section 

3.12.4 for more details on the sequence of events. This bit is set in either of the 

following cases: 
•

After the end bit of the write command. 

•

When write operation is restarted by writing a 1 to Continue Request in the Block 

Gap Control register. 

This bit is cleared in either of the following cases: 
•

After getting the CRC status of the last data block as specified by the transfer count 

(Single and Multiple) In case of ADMA2, transfer count is designated by Descriptor 

Table. 

•

After getting the CRC status of any block where data transmission is about to be 

stopped by a Stop At Block Gap Request. 

During a write transaction, a Block Gap Event interrupt is generated when this bit is 

changed to 0, as the result of the Stop At Block Gap Request being set. This status is 

useful for the Host Driver in determining non DAT line commands can be issued during 

write busy. 
•

1 Transferring data 

•

0 No valid data 

7:3

00h

RO

Reserved.

2

0b

RO

This bit indicates whether one of the DAT lines on 

SD Bus is in use. (a) In the case of read transactions This status indicates whether a 

read transfer is executing on the SD Bus. Changing this value from 1 to 0 generates a 

Block Gap Event interrupt in the Normal Interrupt Status register, as the result of the 

Stop At Block Gap Request being set. Refer to Section 3.12.3 for details on timing. This 

bit shall be set in either of the following cases: 
•

After the end bit of the read command. 

•

When writing a 1 to Continue Request in the Block Gap Control register to restart a 

read transfer. 

This bit shall be cleared in either of the following cases: 
•

When the end bit of the last data block is sent from the SD Bus to the Host 

Controller. In case of ADMA2, the last block is designated by the last transfer of 

Descriptor Table. 

•

When a read transfer is stopped at the block gap initiated by a Stop At Block Gap 

Request. 

The Host Controller shall stop read operation at the start of the interrupt cycle of the 

next block gap by driving Read Wait or stopping SD clock. If the Read Wait signal is 

already driven (due to data buffer cannot receive data), the Host Controller can 

continue to stop read operation by driving the Read Wait signal. It is necessary to 

support Read Wait in order to use suspend / resume function. (b) In the case of write 

transactions This status indicates that a write transfer is executing on the SD Bus. 

Changing this value from 1 to 0 generate a Transfer Complete interrupt in the Normal 

Interrupt Status register. Refer to Section 3.12.4 for sequence details. This bit shall be 

set in either of the following cases: 
•

After the end bit of the write command. 

•

When writing to 1 to Continue Request in the Block Gap Control register to continue 

a write transfer. 

This bit shall be cleared in either of the following cases: 
•

When the SD card releases write busy of the last data block. If SD card does not 

drive busy signal for 8 SD Clocks, the Host Controller shall consider the card drive 

'Not Busy'. In case of ADMA2, the last block is designated by the last transfer of 

Descriptor Table. 

•

When the SD card releases write busy prior to waiting for write transfer as a result 

of a Stop At Block Gap Request. 

(c) Command with busy This status indicates whether a command indicates busy (ex. 

erase command for memory) is executing on the SD Bus. This bit is set after the end bit 

of the command with busy and cleared when busy is de-asserted. Changing this bit from 

1 to 0 generate a Transfer Complete interrupt in the Normal Interrupt Status register. 

Refer Figure 2-11 to Figure 2-13. 
•

1 = DAT Line Active 

•

0 = DAT Line Inactive