Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1878
Datasheet
16.10.3
Block Count Register (BLK_COUNT)—Offset 6h
This register is used to configure the number of data blocks.
Access Method
Default: 0000h
14:12
000b
RW
Host SDMA Buffer Boundary (boundary):
The large contiguous memory space may
not be available in the virtual memory system. To perform long SDMA transfer, SDMA
System Address register shall be updated at every system memory boundary during
SDMA transfer. These bits specify the size of contiguous buffer in the system memory.
The SDMA transfer shall wait at each boundary specified by these fields and the Host
Controller generates the DMA Interrupt to request the Host Driver to update the SDMA
System Address register. At the end of transfer, the Host Controller may issue or may
not issue DMA Interrupt. In particular, DMA Interrupt shall not be issued after Transfer
Complete Interrupt is issued. In case of this register is set to 0 (buffer size = 4K bytes),
lower 12-bit of byte address points data in the contiguous buffer and the upper 20-bit
points the location of the buffer in the system memory. The SDMA transfer stops when
the Host Controller detects carry out of the address from bit 11 to 12. These bits shall
be supported when the SDMA Support in the Capabilities register is set to 1 and this
function is active when the DMA Enable in the Transfer Mode register is set to 1. ADMA
does not use this register.
•
•
000b = 4K bytes (Detects A11 carry out)
•
001b = 8K bytes (Detects A12 carry out)
•
010b = 16K Bytes (Detects A13 carry out)
•
011b = 32K Bytes (Detects A14 carry out)
•
100b = 64K bytes (Detects A15 carry out)
•
101b = 128K Bytes (Detects A16 carry out)
•
110b = 256K Bytes (Detects A17 carry out)
•
111b = 512K Bytes (Detects A18 carry out)
11:0
000h
RW
Transfer Block Size (tr_blk_size):
This register specifies the block size of data
transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. Values ranging from 1 up to
the maximum buffer size can be set. In case of memory, it shall be set up to 512 bytes
(Refer to Implementation Note in Section 1.7.2 Determining Buffer Block Length). It can
be accessed only if no transaction is executing (i.e., after a transaction has stopped).
Read operations during transfers may return an invalid value, and write operations shall
be ignored.
•
•
0800h = 2048 Bytes
•
. . .
•
0200h = 512 Bytes
•
01FFh = 511 Bytes
•
. . .
•
0004h = 4 Bytes
•
0003h = 3 Bytes
•
0002h = 2 Bytes
•
0001h = 1 Byte
•
0000h = No data transfer
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:23, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
blk_c
ount