Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Electrical Specifications
Intel
®
Atom™ Processor E3800 Product Family
194
Datasheet
1.
tDATA_HOLD has a minimum timing for I2C of 0 ns, while the minimum timing for SMBus is 300 ns.
2.
A device will timeout when any clock low exceeds this value.
3.
tSLVCLK_LOWEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the
initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset
itself.
4.
tMSTCLK_LOWEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from start-to-ack, ack-to-ack or ack-to-stop.
Table 141. SMBus Timing
Sym
Parameter
Min
Max
Units
Notes
Figure
t
STOP_START
Bus Tree Time Between Stop and Start
Condition
Condition
4.7
—
µs
t
START_HOLD
Hold Time after (repeated) Start
Condition. After this period, the first clock
is generated.
Condition. After this period, the first clock
is generated.
4.0
—
µs
t
START_SET
Repeated Start Condition Setup Time
4.7
—
µs
t
STOP_SET
Stop Condition Setup Time
4.0
—
µs
t
DATA_HOLD
Data Hold Time
0
—
ns
1
t
DATA_SET
Data Setup Time
250
—
ns
t
DEV_TO
Device Time Out
25
35
ms
2
t
SLVCLK_LOWEXT
Cumulative Clock Low Extend Time (slave
device)
device)
—
25
ms
3
t
MSTCLK_LOWEXT
Cumulative Clock Low Extend Time
(master device)
(master device)
—
10
ms
4
Figure 70. SMBus Transaction
Figure 71. SMBus Timeout
t
LOW
t
RISE
t
FALL
t
HIGH
t
STOP_START
t
START_HOLD
t
START_SET
t
STOP_SET
t
DATA_HOLD
t
DATA_SET
PCU_SMB_DATA
PCU_SMB_CLK
t
SLVCLK_LOWEXT
t
MSTCLK_LOWEXT
t
MSTCLK_LOWEXT
Start
Stop
CLK
ack
CLK
ack
PCU_SMB_DATA
PCU_SMB_CLK