Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

197

1.

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU; DAT ³ 250 ns 

must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2C_CLK signal. 

If such a device does stretch the LOW period of the I2C_CLK signal, it must output the next data bit to the I2C_DATA line 

tr max + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2C_CLK 

line is released

2.

Cb = total capacitance of one bus line in pF.

3.

No Active current source PU on I2C_CLK signals. Rise time is based upon the Pull-up resistor mentioned in the Platform 

Design Guide.

4.

The maximum tHD;DAT could be 3.45 ms and 0.9 ms for Standard-mode and Fast-mode, but must be less than the 

maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the 

LOW period (tLOW) of the I2C_CLK signal. If the clock stretches the I2C_CLK, the data must be valid by the set-up time 

before it releases the clock.

5.

Specification deviates from the minimum time compared to Industrial specification.

t

SU:STA

 

Set-up time for a repeated 

START condition 

4.7 –

0.6  –

0.26

–

µs 

t

HD:DAT 

Data hold time: I

2

C-bus 

devices 

0

–

0

–

0

–

ns

t

SU:DAT 

Data set-up time 

250 –

100  –

50

–

ns  1

t

r

 

Rise time of both I

2

C_DATA 

and I

2

C_CLK signals 

–

1000 

20 + 

0.1C

b

(5)

 

300 –

120

ns 2, 

3

t

f 

Fall time of both I

2

C_DATA 

and I

2

C_CLK signals 

1

300

1

300

1

120

ns 5

t

SU:STO

 

Set-up time for STOP 

condition 

4.0 –

0.6  –

0.26

-

µs 

t

BUF

 

Bus free time between a 

STOP and START condition 

4.7 –

1.3  –

0.5

–

µs 

C

b 

Capacitive load for each 

bus line 

– 130

–

130

-

-

pF 

V

nL

 

Noise margin at the LOW 

level for each connected 

device (including 

hysteresis) 

0.1 

V

DD

 

–

0.1  V

DD

 

–

0.1 

V

DD

 

–

V 

V

nH

 

Noise margin at the HIGH 

level for each connected 

device (including 

hysteresis) 

0.2 

V

DD

 

–

0.2  V

DD

 

–

0.2 

V

DD

 

–

V