Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1996
Datasheet
17.8.42
Enclosure Management Message Format (EM_MF)—Offset 580h
This register is not implemented in VLV.
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0
RSVD
0
DM
DIT
O
MDA
T
DET
O
DS
P
AD
S
E
Bit
Range
Default &
Access
Description
31:29
0b
RO
RSVD0:
Reserved
28:25
Fh
RW/O
DITO Multiplier (DM):
0's based value that specifies the DITO multiplier that the HBA
applies to the specified DITO value, effectively extending the range of DITO from 1ms to
16368ms. A value of 0h indicates a multiplier of 1. A maximum multiplier of 16 may be
applied. The HBA computes the total idle timeout as a product of DM and DITO (i.e.
DITO actual = DITO * DM).
24:15
004h
RW
DEVSLP Idle Timeout (DITO):
This field specifies the amount of the time (in
approximate 1ms granularity) that the HBA shall wait before driving the DEVSLP signal.
14:10
0Ah
RW
DEVSLP Minimum Assertion Time (MDAT):
This field specifies the minimum amount
of time (in 1ms granularity) that the HBA must assert the DEVSLP signal before it may
be de-asserted. The nominal value is 10ms and the minimum is 1ms depending on
device identification information.
9:2
14h
RW
DEVSLP Exit Timeout (DETO):
This field specifies the maximum duration (in
approximate 1ms granularity) from DEVSLP de-assertion until the device is ready to
accept OOB. The nominal value is 20ms while the max value is 255ms depending on
device identification information.
1
1h
RW/O
DEVSLP Present (DSP):
If set to 1, the platform supports DEVSLP on this port. If
cleared to 0, the platform does not support DEVSLP on this port.
0
0h
RW
Aggressive DEVSLP Enable (ADSE):
When this bit is cleared to 0, the HBA does not
enter DEVSLP unless software directed via PxCMD.ICC. This bit shall only be set to 1 if
PxDEVSLP.DSP is set to 1. If this bit is set to 1 and software clears the bit to 0, then the
HBA shall de-assert the DEVSLP signal if asserted.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
EM_MF:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
Bit
Range
Default &
Access
Description
31:0
0h
RO
RSVD:
Reserved.