Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2053
17.18.8
TX_DWORD7 (tx_dword7)—Offset 1Ch
Access Method
Default: 0038383Fh
30:24
1Fh
RW
onswbypass_6_0:
Determines # of slices activated in N-drv when in strong pulling to
CM (after Rx-dtct/ gohighz / stongPD) same slices canot be opend for P-drv and for N-
drv. Determines # of slices for P-drv in All1/All0 DFTs when bypbycomp is not asserted.
In these DFT modes pswpass can be set to the same value as nswbypass
23
0h
RO
reserved519:
reserved
22:16
20h
RW
opswbypass_6_0:
Determines # of slices activated in P-drv when in strong pulling to
CM (after Rx-dtct/ gohighz / stongPD) Determines # of slices for P-drv in All1/All0 DFTs
when bypbycomp is not asserted.
15
0h
RO
reserved518:
reserved
14:8
0h
RO
reserved517:
reserved
7
0h
RW
ocalccont:
initiate calculation of swing-cotrol circuit. While this signal is '1' the
calculation is beeing done consecutively
6:0
0h
RO
reserved516:
reserved
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1
res
er
ved
52
7
res
er
ved
52
6
res
er
ved
52
5
res
er
ved
52
4
res
er
ved
52
3
oslr
ctrl
r2_l_2_
0
oslr
ctrlr
2
_
h
_2_
0
res
er
ved
52
2
os
lrctr
l_l_2_
0
oslr
ctrl
_
h
_2_
0
res
er
ved
52
1
or
2bypass
_5_
0
Bit
Range
Default &
Access
Description
31:30
0h
RO
reserved527:
reserved
29:27
0h
RO
reserved526:
reserved
26:24
0h
RO
reserved525:
reserved
23
0h
RO
reserved524:
reserved
22
0h
RO
reserved523:
reserved