Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2061
Bit
Range
Default &
Access
Description
31:30
0h
RW
ospare1_1_0:
reserved
29
0h
RW
osimmode:
Counter threshold of receive-detect, NTL, strong-common-mode is
shortened dramatically for fast simulation porpuses. (does not impose risk to circuitly
but electrical spec will not met)
28
0h
RW
ontlmodepin2pin:
0 - NTL procedure will be done per pad while both pads are pulled
to the same rail. 1 - NTL procedure will be done per pad while the pads are pulled to
opposite rails.
27
0h
RW
ofrcdatapathdis:
DFT feature to optionaly be used with other registers
26
0h
RW
ofrcdatapathen:
DFT feature to optionaly be used with other registers
25
0h
RW
ofrcdrvbypdis:
DFT feature to optionaly be used with other registers
24
0h
RW
ofrcdrvbypen:
DFT feature to optionaly be used with other registers
23
0h
RW
odfttxclkcaptesten:
Enables the finger capacitor quality check in the DCC block in Tx-
clock block. The test is for shorts between the capacitor terminals.
22
1h
RW
otxdccbyps_l:
Tx DCC Bypass Override Puts DCC (duty cycle correction) circuit in
bypass mode 0 - clock's duty cycle is not fixed
21:19
0h
RW
ofrcnmos32idv_2_0:
change the value iabut_idvpmos32_h[1:0] pushes to txclk
3'b0?? - don't affect the idv comp 3'b100 - pull the idv information to be always at slow
3'b101 - pull the idv information a bit slower. 3'b110 - pull the idv information a bit
faster. 3'b111 - pull the idv information to be always at fast
18:16
0h
RW
ofrcpmos32idv_2_0:
change the value iabut_idvpmos32_h[1:0] pushes to txclk
3'b0?? - don't affect the idv comp 3'b100 - pull the idv information to be always at slow
3'b101 - pull the idv information a bit slower. 3'b110 - pull the idv information a bit
faster. 3'b111 - pull the idv information to be always at fast
15
0h
RW
visa_en:
VISA Enable for the Tx VISA logic
14:12
0h
RW
ovisa1_clksel_2_0:
VISA Clock Select for Lane1. Selects the source synchronous
clock to be used for data being sent on lane1.
11:8
0h
RW
ovisa1_lanesel_3_0:
VISA Lane Select for Lane1. Selects the byte of data to be sent
out on lane1.
7
0h
RW
ovisa_bypass:
VISA Bypass. Allows for signals to be passed asynchronously through
VISA block. Applies to both lane0 and lane1. 0 : Flop signals in local VISA block
(default) 1 : Bypass flops in local VISA block
6:4
0h
RW
ovisa0_clksel_2_0:
VISA Clock Select for Lane0. Selects the source synchronous
clock to be used for data being sent on lane0.
3:0
0h
RW
ovisa0_lanesel_3_0:
VISA Lane Select for Lane0. Selects data byte to be driven out
of VISA-0 byte. Can be either clocked or unclocked data