Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2069
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
re
g_rxpwrfs
m
_pibias
o
ff_dela
y_3_0
cri_s
q
dbexittime
r_o
ve
rr
ide_3_0
cr
i_sqdbe
n
tr
ytime
r_o
ve
rr
ide_5_0
re
g_rx
drc
g
tsqsel_1_0
cri_r
eut
_
S
la
ve
SideDataCheckingEn
cr
i_
sq
d
b
ti
m
er
_
ov
re
n
cr
i_rxpw
rf
sm_tim
er_ovr
en
re
g_rxid
le
cri_rxr
awd
a
ta_sel
cri_dynkalign_eco3302703_m
ode
cri_dynkalign_e
co33027
03_o
vr
en
re
g
_
rxpwrfs
m
_p
ibias
o
ff_o
vrrid
e
cri_r
es
et_kalignlck
cr
i_e
bpt
rrst
cr
i_comdispfix
cr
i_forc
eb
ankhit
cr
i_kalignmode_1_0
cr
i_skpp
roc
d
is
cr
i_elas
ticb
uffer
_
m
as
kdis
Bit
Range
Default &
Access
Description
31:28
0h
RW
reg_rxpwrfsm_pibiasoff_delay_3_0:
Override value for delay (in 2ns increments)
between deassertion of opianclkbufen and opibiasen
27:24
0h
RW
cri_sqdbexittimer_override_3_0:
Rx squelch exit debounce timer
23:18
0h
RW
cri_sqdbentrytimer_override_5_0:
Rx squelch entry debounce timer
17:16
0h
RW
reg_rxdrcgtsqsel_1_0:
Squelch output select
15
0h
RW
cri_reut_SlaveSideDataCheckingEn:
Enable REUT slave side checking while in
loopback slave
14
0h
RW
cri_sqdbtimer_ovren:
Squelch debounce timer override enable
13
0h
RW
cri_rxpwrfsm_timer_ovren:
Rx power management fsm timer override enable
12
0h
RW
reg_rxidle:
Chicken bit to override i_rxidle from controller and keep Rx in P0 or P0s
11
0h
RW
cri_rxrawdata_sel:
When asserted bypass K-align, 10b/8b decoder and Elastic buffer
10
0h
RW
cri_dynkalign_eco3302703_mode:
Kalign Mode Override Value When
cri_dynkalign_eco3302703_ovren is set, this value selects kalignmode 0 - use register
bits cri_kalignmode[1:0] to select kalignmode 1 - select the 4 COM kalign mode'
9
0h
RW
cri_dynkalign_eco3302703_ovren:
Kalign Mode Override Enable Overrides kalign
mode select pin, allowing config bit kalignmode_override_val to select kalignmode.
8
0h
RW
reg_rxpwrfsm_pibiasoff_ovrride:
When asserted selects
reg_rxpwrfsm_pibiasoff_delay[3:0]
7
0h
RW
cri_reset_kalignlck:
When asserted resets Kalign lock indication and Kalign is
performed again. The conditions when this would assert includes and is not restricted to
any power management states (L0s, L1) or polling quiet states etc.
6
0h
RW
cri_ebptrrst:
Global broadcast to all lanes that the Elastic Buffer pointers should be
reset. This is a pulse and will be generated when we need to reset the pointers because
of collision or various other reasons.
5
0h
RW
cri_comdispfix:
Chicken bit to force disparity in dynamic K-align mode