Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

21

1.0

Initial release.

October 2013

1.5

• Updated the table details of the GPIO Signals for GPIO_S0_SC[046], GPIO_S0_SC[047], 

GPIO_S0_SC[048], GPIO_S5[15], GPIO_S5[16], GPIO_S5[17].

• Added table note (SoC Clock Outputs) that Intel recommends 25 MHz. 19.2 MHz is not 

validated.

• De-featured C6IS for all SKUs.
• Updated the table details of the SoC Sx-States to SLPT_S*# for PMC_PLTRST# from 0 or 

1 to High or Low to match platform understanding.

• Remove VCC and VNN from Bay Trail-M/D SoC Power Rail DC Specs & Max Current table.

• Updated the figure and notes of the S0 to S3 to S4/S5 (Power Down) Sequence.
• Updated the table of the S4/S5 to S0 (Power Up) Sequence for t3 parameter from 100 

max to 95 min (no max).

• Updated the table details of the 25 MHz Platform Clock AC Specification.

• Updated 11.1 note on Thermal management support.

• Updated 12.2.2 table title and details for “Supported DDR3L Memory Size Per Rank” and 

“Supported DDR3L SO-DIMM Size”.

• Updated the supported SDIO/SD card bandwidth is up to 400Mbits per seconds.

• Added figure note of the xHCI and EHCI Port Mapping.
• Updated USB configuration register to correctly reflect the power well.

• Updated chapter title to Intel

®

 Platform Trust Technology (PTT).

• Added a note to Platform Clock Support section that Intel recommends 25 MHz as 19.2 

MHz is not validated.

December 2013

2.0

• Updated the 7.2.2 note 4
• OK to swap V1P0A and V1P8A
• Measurement point for timing is 90% (10% on power down)

• Added S3 power spec per measurements
• Added generic clock jitter specs

February 2014