Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
2688
Datasheet
20.5.39
VCCAP—Offset 100h
Virtual Channel Cap Header
Access Method
Default: 13010002h
20.5.40
PVCCAP1—Offset 104h
Port VC Capability
Access Method
Default: 00000001h
Type: 
PCI Configuration Register
(Size: 32 bits)
VCCAP: 
31
28
24
20
16
12
8
4
0
0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
NXT
C
AP
CV
P
C
IEEC
ID
Bit 
Range
Default & 
Access
Description
31:20
130h
RWO
NXTCAP: 
Next Capability Offset (NXTCAP): Points to the next capability header, which 
is the Root Complex Link Declaration Enhanced Capability Header. This register is RWO 
to support removing the Root Complex Topology Capability from the PCI Express 
Extended Capability List. For systems which support the Root Complex Topology 
Capability Structure, boot BIOS should write a 130h to this register, otherwise boot 
BIOS should write a 000h to this register.
19:16
1h
RWO
CV: 
Capability Version (CV): This register is RWO to support removing the PCI Express 
Extended Capabilities from Azalia. For systems which support the PCI Express Virtual 
Channel capability and the Root Complex Topology Capability Structure, boot BIOS 
should write a 1h to this register, otherwise boot BIOS should write a 0h to this register.
15:0
2h
RWO
PCIEECID: 
PCI Express Extended Capability ID (PCIEECID): This register is RWO to 
support removing the PCI Express Extended Capabilities from Azalia. For systems which 
support the PCI Express Virtual Channel capability and the Root Complex Topology 
Capability Structure, boot BIOS should write a 0002h to this register, otherwise boot 
BIOS should write a 0000h to this register.
Type: 
PCI Configuration Register
(Size: 32 bits)
PVCCAP1: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RESE
RVE
D
PA
R
B
T
B
LE
S
RC
RES
E
RVE
D
1
LPV
CCNT
RES
E
RVE
D
2
V
CCNT
Bit 
Range
Default & 
Access
Description
31:12
0h
RO
RESERVED: 
RESERVED