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Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
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Intel
®
 Atom™ Processor E3800 Product Family
2830
Datasheet
21.10.4
reg_CLLATHEADERBIST_type (CLLATHEADERBIST)—Offset Ch
CLLATHEADERBIST - Cache Line Latency Header and BIST
Access Method
Default: 00000000h
21.10.5
reg_BAR_type (BAR)—Offset 10h
BAR -Base Address Register
Access Method
Default: 00000000h
Bit 
Range
Default & 
Access
Description
31:8
040100h
RO
CLASS_CODES: 
Class Code
7:0
00h
RO
RID: 
Revision ID
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
CLLATHEADERBIST: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Re
se
rv
ed
0
MULFNDEV
HE
ADER
TYP
E
LA
TT
IME
R
CA
CH
E
LIN
E_S
IZE
Bit 
Range
Default & 
Access
Description
31:24
00h
RO
Reserved0: 
Reserved
23
0h
RO
MULFNDEV: 
MULFNDEV
22:16
00h
RO
HEADERTYPE: 
Header Type: Implements Type 0 Configuration header.
15:8
00h
RO
LATTIMER: 
Latency Timer:. This register is implemented as R/W with default as 0. 
Similar to other Intel IPs.
7:0
00h
RW
CACHELINE_SIZE: 
Cacheline Size: This register is implemented as R/W with default as 
0. Similar to other Intel IPs.
Type: 
Memory Mapped I/O Register
(Size: 32 bits)
BAR: