Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Introduction
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
29
1.1
Terminology
Term
Description
ACPI
Advanced Configuration and Power Interface
Cold Reset
A Host reset with Power Cycle. See
Table 132
CRT
Cathode Ray Tube
CRU
Clock Reset Unit
DP
Display Port
DTS
Digital Thermal Sensor
EMI
Electro Magnetic Interference
eDP
embedded Display Port
HDMI
High Definition Multimedia Interface. HDMI supports standard, enhanced, or high-
definition video, plus multi-channel digital audio on a single cable. HDMI transmits
all Advanced Television Systems Committee (ATSC) HDTV standards and supports
8-channel digital audio, with bandwidth to spare for future requirements and
enhancements (additional details available at
definition video, plus multi-channel digital audio on a single cable. HDMI transmits
all Advanced Television Systems Committee (ATSC) HDTV standards and supports
8-channel digital audio, with bandwidth to spare for future requirements and
enhancements (additional details available at
IGD
Internal Graphics Unit
Intel
®
TXE
Intel
®
Trusted Execution Engine
LCD
Liquid Crystal Display
LPE
Low Power Engine
MIPI CSI
MIPI Camera Interface Specification
MPEG
Moving Picture Experts Group
MSI
Message Signaled Interrupt. MSI is a transaction initiated outside the host,
conveying interrupt information to the receiving agent through the same path that
normally carries read and write commands.
conveying interrupt information to the receiving agent through the same path that
normally carries read and write commands.
MSR
Model Specific Register, as the name implies, is model-specific and may change
from processor model number (n) to processor model number (n+1). An MSR is
accessed by setting ECX to the register number and executing either the RDMSR
or WRMSR instruction. The RDMSR instruction will place the 64 bits of the MSR in
the EDX: EAX register pair. The WRMSR writes the contents of the EDX: EAX
register pair into the MSR.
from processor model number (n) to processor model number (n+1). An MSR is
accessed by setting ECX to the register number and executing either the RDMSR
or WRMSR instruction. The RDMSR instruction will place the 64 bits of the MSR in
the EDX: EAX register pair. The WRMSR writes the contents of the EDX: EAX
register pair into the MSR.
PCIe*
PCI Express* (PCIe*) is a high-speed serial interface. The PCIe* configuration is
software-compatible with the existing PCI specifications.
software-compatible with the existing PCI specifications.
PWM
Pulse Width Modulation
Rank
A unit of DRAM corresponding to the set of SDRAM devices that are accessed in
parallel for a given transaction. For a 64-bit wide data bus using 8-bit (x8) wide
SDRAM devices, a rank would be eight devices. Multiple ranks can be added to
increase capacity without widening the data bus, at the cost of additional electrical
loading.
parallel for a given transaction. For a 64-bit wide data bus using 8-bit (x8) wide
SDRAM devices, a rank would be eight devices. Multiple ranks can be added to
increase capacity without widening the data bus, at the cost of additional electrical
loading.
SCI
System Control Interrupt. SCI is used in the ACPI protocol.
SDRAM
Synchronous Dynamic Random Access Memory
SERR
System Error. SERR is an indication that an unrecoverable error has occurred on
an I/O bus.
an I/O bus.