Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

319

Aunit Error Logging Register (ADBGERRLOG) This register is used as a means to log 

errors in Aunit. All upstream errors are logged with Port ID. Each error has a bit mask 

that enables the error logging.

Default: 00000000h

Message Bus Register

(Size: 32 bits)

Op Codes:
h - Read, h - Write

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ENABL

E

_ERR_L

O

G

RESE

RVE

D

_0

ERR_BIT_MA

SK

RESE

RVE

D

_1

DOWNSTR

E

AM_VIO

U

PSTRE

AM_PO

R

TID

RESE

RVE

D

_2

U

PSTR

E

AM_VIO

31

0h

RW

Enable error logging for error. When set, the Aunit will latch 

violation information into this register. This bit is cleared upon triggering and must be 

reset by software in order to trigger again.

30

0h

RO

Reserved

29:18

0h

RW

When set enables error logging of the error. 0 disables the error 

logging. Bit 29 IO_length8_notqw_aligned Bit 28 IO_unsupported_length Bit 27 

ecam_unsupported_length Bit 26 ecamcross_dw_boundary Bit 25 mult_tdec_hit Bit 24 

unsupported_iosf_op Bit 23 cfgwrite Bit 22 cfgread Bit 21 iowrite Bit 20 ioread Bit 19 

unsupported_cmd Bit 18 unsupported_vdm

17

0h

RO

Reserved

16:12

0h

RO

Downstream violations Bit 16 - IO request length is 8 but not 

QW aligned Bit 15 - IO request length is not 1, 2, 3, 4, or 8 Bit 14 - ECAM with 

unsupported length Bit 13 - ECAM crosses dw boundary Bit 12 - target decode multiple 

hits

11:8

0h

RO

Port ID for upstream error

7

0h

RO

Reserved

6:0

0h

RO

Upstream violation Bit 6 - received other unsupported IOSF 

transaction that arent translated correctly LTMemRead/Wr, FetchAdd, Swap, CAS Bit 5 - 

received CFGWrite Bit 4 - received CFGRead Bit 3 - received IOWrite Bit 2 - received 

IORead Bit 1 - received unsuccessful completion (e.g. UR, CRS, CA) Bit 0 - received 

unsupported VDM