Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
335
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESE
RVED
_0
DIMM
1_RAN
K
2_SIZE
DIMM1_
PA
R
T
_WID
TH
RESE
RVED
_1
DIMM
0_RAN
K
0_SIZE
DIMM0_
PA
R
T
_WID
TH
RANK3_E
NABLE
RANK2_E
NABLE
RANK1_E
NABLE
RANK0_E
NABLE
MEMOR
Y
_IN
T
ERF
A
CE_WID
TH_32
B
6
4B
RANK_INTERL
E
A
V
E_E
N
ABLE
DRAM_AD
D
RES
S
_HASH_E
N
ABLE
Bit
Range
Default &
Access
Field Name (ID): Description
31:18
0h
RO
RESERVED_0:
Reserved
17:15
0h
RW
DIMM1_RANK2_SIZE:
Configures the memory size of the ranks used by the address
hash function for DIMM1. Note: If the Dunit DIMM Flip bit is set to 1 this field is the rank
size for DIMM0. 0h = 128MB 1h = 256MB 2h = 512MB 3h = 1GB 4h = 2GB 5h = 4GB 6h
= 8GB 7h = Reserved
14:13
0h
RW
DIMM1_PART_WIDTH:
Note: If the Dunit DIMM Flip bit is set to 1 this field is the part
width for DIMM0. 0h: 8-bit 1h: 16-bit 2h: 32-bit 3h: Reserved
12
0h
RO
RESERVED_1:
Reserved
11:9
0h
RW
DIMM0_RANK0_SIZE:
Configures the memory size of the ranks used by the address
hash function for DIMM0. Note: If Dunit DIMM Flip bit is set to 1 this field is the rank size
for DIMM1. 0h = 128MB 1h = 256MB 2h = 512MB 3h = 1GB 4h = 2GB 5h = 4GB 6h =
8GB 7h= Reserved // PnP: Set based on how ranks are populated. Assuming RANK0,1
on DIMM0 are used.
8:7
0h
RW
DIMM0_PART_WIDTH:
Note: If the Dunit DIMM Flip bit is set to 1 this field is the part
width for DIMM1. // PnP: Set based on how ranks are populated. Assuming x16 0h: 8-
bit 1h: 16-bit 2h: 32-bit 3h: Reserved
6
0h
RW
RANK3_ENABLE:
When set Rank3 for DIMM1 is enable Note: If Dunit DIMM Flip bit is
set to 1 this field is the rank enable for rank 1.
5
0h
RW
RANK2_ENABLE:
When set Rank2 for DIMM1 is enable Note: If Dunit DIMM Flip bit is
set to 1 this field is the rank enable for rank 0.
4
0h
RW
RANK1_ENABLE:
When set Rank1 for DIMM0 is enable Note: If Dunit DIMM Flip bit is
set to 1 this field is the rank enable for rank 3.
3
0h
RW
RANK0_ENABLE:
When set Rank0 for DIMM0 is enable Note: If Dunit DIMM Flip bit is
set to 1 this field is the rank enable for rank 2.
2
0h
RW
MEMORY_INTERFACE_WIDTH_32B64B:
When set to 1: Configures the hashing
function for 64b memory interface. When set to 0: Configures the hashing function for
32b memory interface.
1
0h
RW
RANK_INTERLEAVE_ENABLE:
When Set to 1: Enables hashing function to be used
for Dunit Rank Select bits. When Set to 0: Disable the hashing function to be used for
Dunit Rank Select bits. PnP: This has to match the RSIEN in DRP register in Dunit
0
0h
RW
DRAM_ADDRESS_HASH_ENABLE:
When Set to 1: Enables hashing function to be
used for Dunit Bank and Rank Select bits. When Set to 0: Disable the hashing function
to be used for Dunit Bank and Rank Select bits. When disabled the Dunit Bank and Rank
select bits are specified using BBANKMASK And BRANKMASK configuration registers.