Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
342
Datasheet
13.4.6
CUNIT_MSG_CTRL_REG—Offset D0h
Message Control Register (MCR) - provides the message bus command fields. A write
to this register issues a message on the Message Network with the fields specified by
the write data. All byte enables must be enabled when writing this register. The
physical registers reside in the target unit. This register does not reside in the Cunit.
Access Method
Default: 00000000h
13.4.7
CUNIT_MSG_DATA_REG—Offset D4h
Message Data Register (MDR) - provides the means to specify data to be written or
retrieving data that was read during a message operation. For messages with a data
payload, MDR must be written with the data to be sent prior to a write to MCR. For
messages that return data, MDR contains the data read after the write to MCR
completes.
Access Method
Default: 00000000h
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M
E
SSA
G
E
_
O
PC
O
D
E
ME
S
SAGE
_
PO
R
T
M
E
S
S
AG
E_A
DDRES
S_O
FFSET
M
E
S
S
AG
E_WR_BY
T
E_ENA
B
LES
RE
S
E
R
V
E
D
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
00h
WO
MESSAGE_OPCODE:
Opcode for message to be sent out on message network
23:16
00h
WO
MESSAGE_PORT:
Destination PortID for message to be sent out on message network
15:8
00h
WO
MESSAGE_ADDRESS_OFFSET:
Address offset for message to be sent out on message
network
7:4
0h
WO
MESSAGE_WR_BYTE_ENABLES:
Active high byte enables which enable each of the
corresponding bytes in the MDR when high.
3:0
00h
WO
RESERVED:
Reserved
Type:
PCI Configuration Register
(Size: 32 bits)
Offset: