Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

3789

The following is a list of SPI features:

•

Single interrupt line

— Could be assigned to interrupt PCI INT [A] or ACPISIO INT[1]

•

Configurable frame format, clock polarity and clock phase

•

supporting one SPI peripheral only

•

Supports master mode only

•

Receive and transit buffers are both 256x32bits

— The receive buffer has only 1 water mark 

— The transmit buffer has 2 water marks

•

Supports up to 15 Mbps

SPI clock phase and clock polarity overview. 

•

The SSCR1.SPO polarity setting bit determines whether the serial transfer occurs 
on the rising edge of the clock or the falling edge of the clock. 

— When SSCR1.SPO = 0, the inactive or idle state of SIO_SPI_CLK is low.

— When SSCR1.SPO = 1, the inactive or idle state of SIO_SPI_CLK is high.

•

The SSCR1.SPH phase setting bit selects the relationship of the serial clock with the 
slave select signal.

— When SSCR1.SPH = 0, SIO_SPI_CLK is inactive until one cycle after the start of 

a frame and active until 1/2 cycle after the end of a frame.

— When SSCR1.SPH = 1, SIO_SPI_CLK is inactive until 1/2 cycle after the start of 

a frame and active until one cycle after the end of a frame.

Below figure shows an 8-bit data transfer with different phase and polarity settings.

I/O

V1P8S

SPI Chip Select
SPI Chip Select is active low.

O

V1P8S

I

V1P8S