Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

3826

Datasheet

The START BYTE procedure is as follows:

1. Master generates a START condition.

2. Master transmits the START byte (0000 0001).

3. Master transmits the ACK clock pulse. (Present only to conform with the byte 

handling format used on the bus.)

4. No slave sets the ACK signal to 0.

5. Master generates a RESTART (R) condition.

A hardware receiver does not respond to the START BYTE because it is a reserved 
address and resets after the RESTART condition is generated.

To use the I

2

C controller as a master, perform the following steps: 

1. Disable the I

2

C controller by writing 0 (zero) to IC_ENABLE.ENABLE. 

2. Write to the IC_CON register to set the maximum speed mode supported for slave 

operation IC_CON.SPEED and to specify whether the I

2

C controller starts its 

transfers in 7/10 bit addressing mode when the device is a slave 
(IC_CON.IC_10BITADDR_SLAVE). 

3. Write to the IC_TAR register the address of the I

2

C device to be addressed. It also 

indicates whether a General Call or a START BYTE command is going to be 
performed by I

2

C. The desired speed of the I

2

C controller master-initiated 

transfers, either 7-bit or 10-bit addressing, is controlled by the 
IC_TAR.IC_10BITADDR_MASTER bit field. 

4. Write to the IC_HS_MADDR register the desired master code for the I

2

C controller. 

The master code is programmer-defined. 

5. Enable the I

2

C controller by writing a 1 in IC_ENABLE. 

6. Now write the transfer direction and data to be sent to the IC_DATA_CMD register. 

If the IC_DATA_CMD register is written before the I

2

C controller is enabled, the 

Data

Clock

S

1

2

7

8

9

dummy acknowledge 

ACK

Sr

(HIGH)

Start byte 00000001