Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

4084

Datasheet

26.17

SIO I

2

C 5 Memory Mapped I/O Registers

Table 270.

Summary of I

2

C 5 Memory Mapped I/O Registers—BAR

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value

0–3h

4

“I2C Control Register (IC_CON)—Offset 0h” on page 4086

0000007Fh

4–7h

4

“I2C Target Address Register (IC_TAR)—Offset 4h” on page 4087

00001055h

8–Bh

4

“I2C Slave Address Register (IC_SAR)—Offset 8h” on page 4088

00000055h

C–Fh

4

“I2C High Speed Master Mode Code Address Register (IC_HS_MADDR)—Offset

Ch” on page 4088

00000001h

10–13h

4

“I2C Rx/Tx Data Buffer and Command Register (IC_DATA_CMD)—Offset 10h”

00000000h

14–17h

4

“Standard Speed I2C Clock SCL High Count Register (IC_SS_SCL_HCNT)—

Offset 14h” on page 4090

00000190h

18–1Bh

4

“Standard Speed I2C Clock SCL Low Count Register (IC_SS_SCL_LCNT)—Offset

18h” on page 4090

000001D6h

1C–1Fh

4

“Fast Speed I2C Clock SCL High Count Register (IC_FS_SCL_HCNT)—Offset

1Ch” on page 4091

0000003Ch

20–23h

4

“Fast Speed I2C Clock SCL Low Count Register (IC_FS_SCL_LCNT)—Offset 20h”

00000082h

24–27h

4

“High Speed I2C Clock SCL High Count Register (IC_HS_SCL_HCNT)—Offset

24h” on page 4092

0000000Ch

28–2Bh

4

“High Speed I2C Clock SCL Low Count Register (IC_HS_SCL_LCNT)—Offset

28h” on page 4093

00000020h

2C–2Fh

4

“I2C Interrupt Status Register (IC_INTR_STAT)—Offset 2Ch” on page 4094

00000000h

30–33h

4

“I2C Interrupt Mask Register (IC_INTR_MASK)—Offset 30h” on page 4095

000008FFh

34–37h

4

“I2C Raw Interrupt Status Register (IC_RAW_INTR_STAT)—Offset 34h” on

00000000h

38–3Bh

4

“I2C Receive FIFO Threshold Register (IC_RX_TL)—Offset 38h” on page 4097

00000010h

3C–3Fh

4

“I2C Transmit FIFO Threshold Register (IC_TX_TL)—Offset 3Ch” on page 4098

00000010h

40–43h

4

“Clear Combined and Individual Interrupt Register (IC_CLR_INTR)—Offset 40h”

00000000h

44–47h

4

“Clear RX_UNDER Interrupt Register (IC_CLR_RX_UNDER)—Offset 44h” on

00000000h

48–4Bh

4

“Clear RX_OVER Interrupt Register (IC_CLR_RX_OVER)—Offset 48h” on

00000000h

4C–4Fh

4

“Clear TX_OVER Interrupt Register (IC_CLR_TX_OVER)—Offset 4Ch” on

00000000h

50–53h

4

“Clear RD_REQ Interrupt Register (IC_CLR_RD_REQ)—Offset 50h” on

00000000h

54–57h

4

“Clear TX_ABRT Interrupt Register (IC_CLR_TX_ABRT)—Offset 54h” on

00000000h

58–5Bh

4

“Clear RX_DONE Interrupt Register (IC_CLR_RX_DONE)—Offset 58h” on

00000000h

5C–5Fh

4

“Clear ACTIVITY Interrupt Register (IC_CLR_ACTIVITY)—Offset 5Ch” on

00000000h

60–63h

4

“Clear STOP_DET Interrupt Register (IC_CLR_STOP_DET)—Offset 60h” on

00000000h