Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
SIO – High Speed UART
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4175
27.3
Use
Each UART has a transmit FIFO and a receive FIFO, each FIFO holding 64 characters of
data. Three separate methods move data into and out of the FIFOs: interrupts, DMA,
and polled.
data. Three separate methods move data into and out of the FIFOs: interrupts, DMA,
and polled.
27.3.1
DMA Mode Operation
27.3.1.1
Receiver DMA
The data transfer from the HSUART to host memory is controlled by the DMA write
channel. To configure the channel in write mode, channel direction in the channel
control register needs to be programmed to “1”. The software need to program the
descriptor start address register, descriptor transfer size register, and descriptor control
register before starting the channel using the channel active bit in the channel control
register.
channel. To configure the channel in write mode, channel direction in the channel
control register needs to be programmed to “1”. The software need to program the
descriptor start address register, descriptor transfer size register, and descriptor control
register before starting the channel using the channel active bit in the channel control
register.
27.3.1.2
Transmit DMA
The data transfer from host memory to HSUART is controlled by DMA read channel. To
configure the channel in read mode, channel direction in the channel control register
needs to be programmed to “0”. The software need to program the descriptor start
address register, descriptor transfer size register, and descriptor control register before
starting the channel using the channel active bit in the channel control register.
configure the channel in read mode, channel direction in the channel control register
needs to be programmed to “0”. The software need to program the descriptor start
address register, descriptor transfer size register, and descriptor control register before
starting the channel using the channel active bit in the channel control register.
27.3.1.3
Removing Trailing Bytes in DMA Mode
When the number of entries in the Receive FIFO is less than its trigger level, and no
additional data is received, the remaining bytes are called Trailing bytes. These are
DMAed out by the DMA as it has visibility into the FIFO Occupancy register.
additional data is received, the remaining bytes are called Trailing bytes. These are
DMAed out by the DMA as it has visibility into the FIFO Occupancy register.
27.3.2
FIFO Polled-Mode Operation
With the FIFOs enabled (IIR_FCR.IID0_FIFOE bit set to 1), clearing IER_DLH[7] and
IER_DLH[4:0] puts the serial port in the FIFO Polled Operation mode. Because the
receiver and the transmitter are controlled separately, either one or both can be in
Polled Operation mode. In this mode, software checks Receiver and Transmitter status
using the Line Status Register (LSR). The processor polls the following bits for Receive
and Transmit Data Service.
IER_DLH[4:0] puts the serial port in the FIFO Polled Operation mode. Because the
receiver and the transmitter are controlled separately, either one or both can be in
Polled Operation mode. In this mode, software checks Receiver and Transmitter status
using the Line Status Register (LSR). The processor polls the following bits for Receive
and Transmit Data Service.
27.3.2.1
Receive Data Service
The processor checks data ready (LSR.DR) bit which is set when 1 or more bytes
remains in the Receive FIFO or Receive Buffer Register (RBR_THR_DLL).
remains in the Receive FIFO or Receive Buffer Register (RBR_THR_DLL).
27.3.2.2
Transmit Data Service
The processor checks transmit data request LSR.THRE bit, which is set when the
transmitter needs data.
transmitter needs data.