Intel E3815 FH8065301567411 Data Sheet

Product codes

FH8065301567411

Intel

Atom™ Processor E3800 Product Family

Datasheet

4187

27.6

SIO HSUART 0 Memory Mapped I/O Registers

Table 278.

Summary of HSUART 1 Memory Mapped I/O Registers—BAR

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value

0–3h

“Receive Buffer Register/Transmit Holding Register/Divisor Latch (Low).

(RBR_THR_DLL)—Offset 0h” on page 4188

00000000h

4–7h

“Divisor Latch (High)/ Interrupt Enable Register. (IER_DLH)—Offset 4h” on

page 4189

00000000h

8–Bh

“Interrupt Identification Register and FIFO Control Register. (IIR_FCR)—Offset

8h” on page 4190

00000001h

C–Fh

“Line Control Register (LCR)—Offset Ch” on page 4191

00000000h

10–13h

“Modem Control Register (MCR)—Offset 10h” on page 4192

00000000h

14–17h

“Line Status Register (LSR)—Offset 14h” on page 4193

00000060h

18–1Bh

“Modem Status Register (MSR)—Offset 18h” on page 4195

00000000h

1C–1Fh

“Scratchpad Register (SCR)—Offset 1Ch” on page 4196

00000000h

30–33h

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 0

(SRBR_STHR0)—Offset 30h” on page 4197

00000000h

34–37h

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 1

(SRBR_STHR1)—Offset 34h” on page 4198

00000000h

38–3Bh

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 2

(SRBR_STHR2)—Offset 38h” on page 4198

00000000h

3C–3Fh

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 3

(SRBR_STHR3)—Offset 3Ch” on page 4199

00000000h

40–43h

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 4

(SRBR_STHR4)—Offset 40h” on page 4199

00000000h

44–47h

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 5

(SRBR_STHR5)—Offset 44h” on page 4200

00000000h

48–4Bh

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 6

(SRBR_STHR6)—Offset 48h” on page 4200

00000000h

4C–4Fh

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 7

(SRBR_STHR7)—Offset 4Ch” on page 4201

00000000h

50–53h

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 8

(SRBR_STHR8)—Offset 50h” on page 4201

00000000h

54–57h

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 9

(SRBR_STHR9)—Offset 54h” on page 4202

00000000h

58–5Bh

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 10

(SRBR_STHR10)—Offset 58h” on page 4202

00000000h

5C–5Fh

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 11

(SRBR_STHR11)—Offset 5Ch” on page 4203

00000000h

60–63h

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 12

(SRBR_STHR12)—Offset 60h” on page 4203

00000000h

64–67h

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 13

(SRBR_STHR13)—Offset 64h” on page 4204

00000000h

68–6Bh

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 14

(SRBR_STHR14)—Offset 68h” on page 4204

00000000h

6C–6Fh

“Shadow Receive Buffer Register and Shadow Transmit Holding Register 15

(SRBR_STHR15)—Offset 6Ch” on page 4205

00000000h

70–73h

“FIFO Access Register (FAR)—Offset 70h” on page 4205

00000000h