Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
422
Datasheet
14.9.4
HDR—Offset Ch
Header Type
Access Method
Default: 00000000h
14.9.5
GTTMMADR_LSB—Offset 10h
Gfx Memory Mapped Address Range. This is the base address for all memory mapped 
registers and GTT table. SOXi Context Save/Restore : Yes This register requests 
allocation for the combined Graphics Translation Table Modification Range and Memory 
Mapped Range. The range requires 4 MB combined for MMIO and Global GTT aperture, 
with 512K of that used by MMIO and 2MB used by GTT. GTTADR will begin at 
(GTTMMADR + 2 MB) while the MMIO base address will be the same as GTTMMADR. For 
the Global GTT, this range is defined as a memory BAR in graphics device config space. 
It is an alias into which software is required to write Page Table Entry values (PTEs). 
Software may read PTE values from the global Graphics Translation Table (GTT). PTEs 
cannot be written directly into the global GTT memory area. The allocation is for 4MB 
and the base address is defined by bits [35:22]. 
7:0
00000000b
RO
REVISION_ID (REVISION_ID_0): 
RID: value of strapRID[7:0] input pin to GVD
Bit 
Range
Default & 
Access
Description
Type: 
PCI Configuration Register
(Size: 32 bits)
Power Well: 
Core
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
_0
M
U
LT
I_
FU
N
C
TI
O
N
_
S
TA
TU
S_
1
HE
AD
E
R
_CO
D
E_2
RSV
D
_3
Bit 
Range
Default & 
Access
Description
31:24
00h
RO
RSVD (RSVD_0): 
Reserved
23
0b
RO
MULTI_FUNCTION_STATUS (MULTI_FUNCTION_STATUS_1): 
MFUNC: Integrated 
graphics is a single function
22:16
00h
RO
HEADER_CODE (HEADER_CODE_2): 
HDR: Indicates a type 0 configuration space 
header format
15:0
0000h
RO
RSVD (RSVD_3): 
Reserved