Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4287
28.8
SIO PWM 1 Memory Mapped I/O Registers
28.8.1
PWM Control Register (PWMCTRL)—Offset 0h
Access Method
Default: 00010000h
28.8.2
Software Reset (RESETS)—Offset 804h
Access Method
Table 285.
Summary of PWM 1 Memory Mapped I/O Registers—BAR
Offset
Size
(Bytes)
Register Name (Register Symbol)
Default
Value
0–3h
4
00010000h
804–807h
4
00000000h
808–80Bh
4
00000010h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:30, F:2] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PWM_E
N
A
B
LE
PWM
_
SW_
U
PDA
T
E
RS
VD0
PWM_BAS
E
_UNIT
PW
M
_
ON_T
IME
_
D
IV
ISO
R
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
PWM Enable (PWM_ENABLE):
•
•
0 = Disable PWM Output
•
1 = Enable PWM Output
30
0b
RW
PWM Software Update (PWM_SW_UPDATE):
Indication that there is an update to
PWM settings pending. SW sets this bit to 1 when updating the PWM_base_unit or
PWM_on_time_divisor fields. The PWM module will apply the new settings at the end of
the current cycle and reset this bit.
•
•
0 = No updates pending
•
1 = Update pending
29:24
0b
RO
RSVD0:
Reserved
23:8
0100h
RW
PWM Base Unit (PWM_BASE_UNIT):
Base unit register. Unsigned 8 integer bits, 8
fraction bits. Used to determine PWM output frequency.
7:0
00h
RW
PWM On Time Divisor (PWM_ON_TIME_DIVISOR):
PWM duty cycle = PWM_on-
time_divisor/256.