Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

4311

30.6

PCU PMC Memory Mapped I/O Registers

Table 293.

Summary of PCU iLB PMC Memory Mapped I/O Registers—

PMC_BASE_ADDRESS

Offset

Size

Register ID—Description

Default

Value

0h

4

“PRSTS - Power and Reset Status (PRSTS)—Offset 0h” on page 4312

00000000h

8h

4

“PM_CFG - Power Management Configuration (PMC_CFG)—Offset 8h” on page 4313

00000000h

Ch

4

“VLV_PM_STS - VLV Power Management Status (VLV_PM_STS)—Offset Ch” on

00000000h

10h

4

“MTPMC - Message to PMC (MTPMC)—Offset 10h” on page 4316

00000000h

20h

4

“General PM Configuration 1 (GEN_PMCON1)—Offset 20h” on page 4316

00004004h

24h

4

“General PM Configuration 2 (GEN_PMCON2)—Offset 24h” on page 4319

00000000h

28h

4

“MFPMC - Message from PMC (MFPMC)—Offset 28h” on page 4320

00000000h

2Ch

4

“SEC_STS - SEC Status (SEC_STS)—Offset 2Ch” on page 4321

00000000h

30h

4

“Configured Revision ID (CRID)—Offset 30h” on page 4321

00000000h

34h

4

“Function Disable (FUNC_DIS)—Offset 34h” on page 4322

00000000h

38h

4

“Function Disable 2 (FUNC_DIS_2)—Offset 38h” on page 4323

00000000h

3Ch

4

“S0ix wake enable (S0IX_WAKE_EN)—Offset 3Ch” on page 4323

00FFFFFFh

40h

4

“S0ix wake Status (S0IX_WAKE_STS)—Offset 40h” on page 4325

00000000h

44h

4

“S0ix control (S0IX_CTL)—Offset 44h” on page 4326

00000050h

48h

4

“ETR - Extended Test Mode Register (ETR)—Offset 48h” on page 4327

00230000h

50h

4

“VLT - Voltage Detect Register (VLT)—Offset 50h” on page 4328

00000000h

58h

4

“GPIO_ROUT - GPIO_ROUT register (GPIO_ROUT)—Offset 58h” on page 4328

00000000h

60h

4

“PLT_CLK_CTL_0 - Platform Clock Control 0 (PLT_CLK_CTL_0)—Offset 60h” on

00000003h

64h

4

“PLT_CLK_CTL_1 - Platform Clock Control 1 (PLT_CLK_CTL_1)—Offset 64h” on

00000003h

68h

4

“PLT_CLK_CTL_2 - Platform Clock Control 2 (PLT_CLK_CTL_2)—Offset 68h” on

00000003h

6Ch

4

“PLT_CLK_CTL_3 - Platform Clock Control 3 (PLT_CLK_CTL_3)—Offset 6Ch” on

00000003h

70h

4

“PLT_CLK_CTL_4 - Platform Clock Control 4 (PLT_CLK_CTL_4)—Offset 70h” on

00000003h

74h

4

“PLT_CLK_CTL_5 - Platform Clock Control 5 (PLT_CLK_CTL_5)—Offset 74h” on

00000003h

80h

4

“S0IR_TMR - S0I Ready Residency Timer (S0IR_TMR)—Offset 80h” on page 4333

00000000h

84h

4

“S0I1_TMR - S0I1 Residency Timer (S0I1_TMR)—Offset 84h” on page 4333

00000000h

88h

4

“S0I2_TMR - S0I2 Residency Timer (S0I2_TMR)—Offset 88h” on page 4334

00000000h

8Ch

4

“S0I3_TMR - S0I3 Residency Timer (S0I3_TMR)—Offset 8Ch” on page 4334

00000000h

90h

4

“S0_TMR - S0 Residency Timer (S0_TMR)—Offset 90h” on page 4335

00000000h

98h

4

“PSS - Power island Power Status (PSS)—Offset 98h” on page 4335

00000000h

A0h

4

“D3_STS_0 - D3 Status register 0 (D3_STS_0)—Offset A0h” on page 4336

00000000h

A4h

4

“D3_STS_1 - D3 Status register 1 (D3_STS_1)—Offset A4h” on page 4336

00000000h