Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
436
Datasheet
14.9.23
VCID—Offset B0h
Vendor Capability ID.SOXi Context Save/Restore : Yes
Access Method
Default: 01070009h
14.9.24
VC—Offset B4h
Vendor Capabilities. Any SKU related fuses would be added here.SOXi Context Save/
Restore : Not required
Access Method
7:1
00h
RO
RSVD (RSVD_0):
Reserved (RSVD):
0
0b
RW/1S
INIT_FLR (INIT_FLR_1):
Initiate Function Level Reset (INIT_FLR): A write of 1b
initiates Function Level Reset (FLR). FLR requirements are defined in the PCI Express
Base Specification. Registers and state information that do not apply to conventional PCI
are exempt from the FLR requirements given there. Once written 1, FLR will be initiated.
During FLR, a read will return 1?s since device 2 reads abort. Once FLR completes,
hardware will clear the bit to 0.
Bit
Range
Default &
Access
Description
Type:
PCI Configuration Register
(Size: 32 bits)
VCID:
Power Well:
Core
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
VERS
ION_0
LENGTH
_1
NEXT
_C
AP
ABILITY_POINTER_2
CA
PA
BILITY
_ID
_
CID
_
3
Bit
Range
Default &
Access
Description
31:24
01h
RO
VERSION (VERSION_0):
VS: Identifies this as the first revision of the CAPID register
definition
23:16
07h
RO
LENGTH (LENGTH_1):
LEN: this field has the value of 07h to indicate structure length
(8 bytes)
15:8
00h
RW/O
NEXT_CAPABILITY_POINTER (NEXT_CAPABILITY_POINTER_2):
00 indicates
capability list ends here. This register should be programmed by BIOS during boot-up.
Once written, this register becomes Read_Only. This register can only be cleared by a
Reset.Write-once allowing the capability list to be changed.
7:0
09h
RO
CAPABILITY_ID_CID (CAPABILITY_ID_CID_3):
Identifies this as a vendor
dependent capability pointers