Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

4366

Datasheet

All SPI signals are tri-stated with 20k ohm internal weak pull-up until 
PMC_CORE_PWROK is asserted.

The SPI controller supports up to two SPI Flash devices using two separate chip select 
pins. Each SPI Flash device can be up to 16 MB. The SoC SPI interface supports 
20 MHz, 33 MHz and 50 MHz SPI Flash devices. No other types of SPI devices are 
supported.

Communication on the SPI bus is done with a Master – Slave protocol. The Slave is 
connected to the SoC and is implemented as a tri-state bus.

When GCS.BBS = 00b, LPC is selected as the location for BIOS. The SPI Flash may still 
contain data and firmware for other SoC functionality.

When GCS.BBS =11b and a SPI device is detected by the SoC, LPC based BIOS Flash is 
disabled.

The SPI controller has two operational modes, Non-Descriptor and Descriptor.

If no valid signature is read (either because there is no SPI Flash, or there is an SPI 
Flash with no valid descriptor), the Flash Controller will operate in a Non-Descriptor 
mode.

The following features are not supported in Non-Descriptor mode:

PCU_SPI_CLK

O

V1P8A

SPI Clock: When the bus is idle, the owner will drive the 
clock signal low.

PCU_SPI_CS[0]#

O

V1P8A

SPI Chip Select 0: Used as the SPI bus request signal for 
the first SPI Flash device.

PCU_SPI_CS[1]#

O

V1P8A

SPI Chip Select 1: Used as the SPI bus request signal for 
the second SPI Flash devices.
This signal is muxed and may be used by other functions.

PCU_SPI_MISO

I

V1P8A

SPI Master IN Slave OUT: Data input pin for the SoC.

PCU_SPI_MOSI

I/O

V1P8A

SPI Master OUT Slave IN: Data output pin for the SoC. 
Operates as a second data input pin for the SoC when in 
Single Input, Dual Output Fast Read mode.