Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
4542
Datasheet
35.7
PCU iLB LPC BIOS Control Memory Mapped I/O Registers
35.7.1
GCS (RCRB_GENERAL_CONTROL)—Offset 0h
General Control and Status - contains BIOS configuration and status
Access Method
Default: 00000000h
Table 324.
Summary of PCU iLB LPC BIOS Control Memory Mapped I/O Registers—
RCRB_BASE_ADDRESS
Offset
Size
Register ID—Description
Default
Value
0h
4
00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
RCRB_GENERAL_CONTROL:
RCRB_BASE_ADDRESS Type:
PCI Configuration Register (Size:
32 bits)
RCRB_BASE_ADDRESS Reference:
RCRB_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + F0h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD0
BBS
ize
RS
VD1
BB
S
RS
VD2
TS
BILD
Bit
Range
Default &
Access
Description
31
0b
RO
RSVD0:
Reserved
30:29
X
RO
Boot Block Size (BBSize):
This field determines the size of the BIOS boot block.
Default is controlled by 'Boot Block Size' soft strap. 00 : 64KB (Default) : Invert A16 if
Top Swap is enabled 01 : 128KB : Invert A17 if Top Swap is enabled 10 : 256KB : Invert
A18 if Top Swap is enabled 11 : Reserved This soft strap only applies when booting from
SPI. Boot from LPC (FWH) only supports a 64KB boot block size (Invert A16) and this
soft strap value is a don't care.
28:12
0b
RO
RSVD1:
Reserved
11:10
X
RW
Boot BIOS Straps (BBS):
This field determines the destination of accesses to the
BIOS memory range. Default is controlled by 'Boot BIOS Straps' pin strap. 00 LPC 01
Reserved 10 Reserved 11 SPI The value in this field can be overwritten by software as
long as the BIOS Interface Lock-Down (bit 0) is not set.
9:2
0b
RO
RSVD2:
Reserved
1
X
RW
Top Swap (TS):
When set, PCU EP will invert either A16, A17, or A18 for cycles going
to the BIOS space (but not the feature space) in the FWH. When cleared, PCU EP will not
invert A16. If booting from LPC (FWH), then the Boot Blook size is 64KB and A16 is
inverted if Top Swap is enabled. If booting from SPI, then the BOOT_BLOCK_SIZE soft
strap determines if A16, A17, or A18 should be inverted if Top Swap is enabled. If Top-
Swap pin-strap is active, then this bit cannot be cleared by software. This bit should be
kept in RTC well and should be reset only by SRTCRST_b
0
0h
RW
BIOS Interface Lock-Down (BILD):
When set, prevents GCS.TS and GCS.BBS from
being changed. This bit can only be written from 0 to 1 once.