Intel E3815 FH8065301567411 Data Sheet

Product codes

FH8065301567411

Intel

Atom™ Processor E3800 Product Family

Datasheet

5045

39.9

PCU iLB GPIO S5 IO Addressed Registers

Table 339.

Summary of PCU iLB GPIO S5 IO Registers—GBASE + 80h

Offset

Size

(Bytes)

Register Name (Register Symbol)

Default

Value

0–3h

“Sus Use Select 1 (cfio_ioreg_SUS_USE_SEL_31_0_)—Offset 0h” on page 5046

00000000h

4–7h

“Sus Io Select 1 (cfio_ioreg_SUS_IO_SEL_31_0_)—Offset 4h” on page 5047

00000000h

8–Bh

“Sus Gpio Level 1 (cfio_ioreg_SUS_GP_LVL_31_0_)—Offset 8h” on page 5048

00000000h

C–Fh

“Sus Trigger Positive Edge Enable 1 (cfio_ioreg_SUS_TPE_31_0_)—Offset Ch”

on page 5049

00000000h

10–13h

“Sus Trigger Negative Edge Enable 1 (cfio_ioreg_SUS_TNE_31_0_)—Offset

10h” on page 5050

00000000h

14–17h

“Sus Trigger Status 1 (cfio_ioreg_SUS_TS_31_0_)—Offset 14h” on page 5050

00000000h

18–1Bh

“Sus Wake Enable 1 (cfio_ioreg_SUS_WAKE_EN_31_0_)—Offset 18h” on

page 5052

00000000h

20–23h

“Sus Use Select 2 (cfio_ioreg_SUS_USE_SEL_43_32_)—Offset 20h” on

page 5053

00000000h

24–27h

“Sus Io Select 2 (cfio_ioreg_SUS_IO_SEL_43_32_)—Offset 24h” on page 5053

00000000h

28–2Bh

“Sus Gpio Level 2 (cfio_ioreg_SUS_GP_LVL_43_32_)—Offset 28h” on

page 5054

00000000h

2C–2Fh

“Sus Trigger Positive Edge Enable 2 (cfio_ioreg_SUS_TPE_43_32_)—Offset 2Ch”

on page 5055

00000000h

30–33h

“Sus Trigger Negative Edge Enable 2 (cfio_ioreg_SUS_TNE_43_32_)—Offset

30h” on page 5056

00000000h

34–37h

“Sus Trigger Status (cfio_ioreg_SUS_TS_43_32_)—Offset 34h” on page 5057

00000000h

38–3Bh

“Sus Wake Enable 2 (cfio_ioreg_SUS_WAKE_EN_43_32_)—Offset 38h” on

page 5058

00000000h