Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

5282

Datasheet

The interrupt decoder is responsible for receiving interrupt messages from other 
devices in the SoC and decoding them for consumption by the interrupt router, the 

 and/or the 

The interrupt router is responsible for mapping each incoming interrupt to the 
appropriate PIRQx, for consumption by the 

The interrupt decoder receives interrupt messages from devices in the SoC. These 
interrupts can be split into two primary groups:

•

For consumption by the interrupt router

•

For consumption by the 8259 PIC

When a PCI-mapped device in the SoC asserts or de-asserts an INT[A:D] interrupt, an 
interrupt message is sent to the decoder. This message is decoded to indicate to the 
interrupt router which specific interrupt is asserted or de-asserted and which device the 
INT[A:D] interrupt originated from.

When a device in the SoC asserts or de-asserts a legacy interrupt (IRQ), an interrupt 
message is sent to the decoder. This message is decoded to indicate to the 8259 PIC, 
which specific interrupt (IRQ[3, 14 or 15]) was asserted or de-asserted.

The interrupt router aggregates the INT[A:D] interrupts for each PCI-mapped device in 
the SoC, received from the interrupt decoder, and the INT[A:D] interrupts direct from 
the Serialized IRQ controller. It then maps these aggregated interrupts to 8 PCI based 
interrupts: PIRQ[A:H]. This mapping is configured using the IR[31:0] registers.

PCI based interrupts PIRQ[A:H] are then available for consumption by either the 8259 
PICs or the IO-APIC, depending on the configuration of the 8 PIRQx Routing Control 
Registers: PIRQA, PIQRB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH.