Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

5306

Datasheet

Slave Operational Control Word 3

Default: 22h

Slave Initialization Command Word 4

Default: 01h

1:0

X

WO

These bits must be programmed to zero.

I/O Register

(Size: 8 bits)

7

4

0

0

0

1

0

0

0

1

0

RE

S

E

R

V

E

D

SMM

ES

M

M

O3S

PMC

RRC

7

0b

RO

Reserved. Must be 0.

6

0b

WO

Special Mask Mode (SMM): If this bit is set, the Special Mask Mode can be used 

by an interrupt service routine to dynamically alter the system priority structure while 

the routine is executing, through selective enabling/ disabling of the other channel's 

mask bits. Bit 6, the ESMM bit, must be set for this bit to have any meaning.

5

1b

WO

Enable Special Mask Mode (ESMM): When set, the SMM bit is enabled to set or 

reset the Special Mask Mode. When cleared, the SMM bit becomes a don't care.

4:3

X

WO

OCW3 Select (O3S): When selecting OCW3, bits 4:3 = 01

2

X

WO

Poll Mode Command (PMC): When cleared, poll command is not issued. When set, 

the next I/O read to the interrupt controller is treated as an interrupt acknowledge 

cycle. An encoded byte is driven onto the data bus, representing the highest priority 

level requesting service.

1:0

10b

WO

Register Read Command (RRC): These bits provide control for reading the ISR and 

Interrupt IRR. When bit 1=0, bit 0 will not affect the register read selection. Following 

ICW initialization, the default OCW3 port address read will be read IRR. To retain the 

current selection (read ISR or read IRR), always write a 0 to bit 1 when programming 

this register. The selected register can be read repeatedly without reprogramming 

OCW3. To select a new status register, OCW3 must be reprogrammed prior to 

attempting the read. 00 No Action 01 No Action 10 Read IRQ Register 11 Read IS 

Register

I/O Register

(Size: 8 bits)