Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
548
Datasheet
14.10.98 MIPIC_DEVICE_READY_REG—Offset B800h
MIPI C Device Ready Register
Access Method
Default: 00000000h
14.10.99 MIPIC_INTR_STAT_REG—Offset B804h
mipi C intrrupt state registr
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
0b
RW
RESERVED:
Reserved.
7:0
0b
RW
READ_DATA_VALID:
Each bit corresponds to presence of valid data in the registers
above. When data is returned from the panel, H/W will write into these registers in
sequence, and set the corresponding valid bit.
When S/W issues a write '1 to the registers, this bit is cleared
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SERV
ED
B
U
S
_
PO
SSE
S
S
IO
N
ULPS
_S
TA
TE
D
E
V
ICE
_RE
A
DY
_
Bit
Range
Default &
Access
Field Name (ID): Description
31:4
0b
RW
RESERVED:
Reserved.
3
0b
RW
BUS_POSSESSION:
mipi C Bus Possession
2:1
0b
RW
ULPS_STATE:
mipi C ULPS state
0
0b
RW
DEVICE_READY_:
Set by the processor to inform that device is ready
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h