Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

577

mipi C stop state stall

Default: 00000000h

31:16

0b

RW

Low power to high speed switching time in terms byte clock 

(txbyteclkhs). This value is based on the byte clock (txbyteclkhs) and low power clock 

frequency (txclkesc). Typical value - Number of byte clocks required to switch from low 

power mode to high speed mode after txrequesths_clk is asserted. 

Current Value is ah = 10 txbyteclkhs

15:0

0b

RW

High speed to low power switching time in terms byte clock 

(txbyteclkhs). This value is based on the byte clock (txbyteclkhs) and low power clock 

frequency (txclkesc). Typical value - Number of byte clocks request to switch from high 

speed mode to low power mode after txrequesths_clk is de-asserted. 

Current Value is 14h = 20 txbyteclkhs

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RE

SERV

ED

MIPIC_

ST

O

P_S

TA

TE

_S

TA

LL_CO

UNTE

R

31:8

0b

RW

reserved

7:0

0b

RW

Delay between (stall the stop state signal) 

the data transfer is increased based on this counter value. This counter is calculated 

from txclkesc. Note: If processor programs this register then it needs to reprogram the 

high_low_ switch counter in B844h and lp_equivalent_byteclk reg in B860h to 

compensate this delay. High_low_switch_count B844h: High to low switch counter = 

Actual High to low switch + stop_sta_stall_reg value * Low power clock equivalence 

value in terms of byte clock LP equivalent byteclk register B860h: LP equivalent byteclk 

value = txclkesc time/ txbyteclk time * (105 + stop_sta_stall_reg value) / 105 Minimum 

time of Low Power short packet transfer = 105 txclkesc