Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

610

Datasheet

Pipe A PSR status register

Default: 00000000h

4:2

0b

RW

b011-111: reserved. 

b010: PSR with HW timer. HW timer decides PSR active entry point. PSR active state 

exits upon MMIO write registers that may change the frame buffer. 

b001: PSR with SW timer. In this mode, SW will keep track of idle frames and buffer 

modification in the driver and explicitly specify the entry and exit PSR active state point.  

b000: PSR manual (debug) mode. All of PSR state transitions and SDP content is 

managed by SW driver. SW is responsible to change SDP content for every frame with 

appropriate values to keep PSR panel in synchronized states.

1

0b

RW

If assert all PSR functions are reset back to PSR inactive state. When it 

needs to resynchronize source and sync, SW writes 0x2 to DPCD register 600h and to 

this bit to get system back to PSR active states. This bit is self clear.

0

0b

RW

Panel Self-refresh is enabled. When it is asserted PSR is enabled and 

operate in one of the mode that specified by PSR mode.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISPLA

Y

_

LO

CAL_S

TANDBY_S

TA

T

E

RESE

RVED

REPEA

T

_FRAME_COUNTE

R

RES

E

RVE

D

_1

SDP

_

SE

NT

P

S

R_IN_

T

RANSIT

IO

N

RES

E

RVE

D

_2

PS

R_LAS

T

_ST

A

TE

PSR

_

CURRENT_S

TA

TE

31:30

0b

RO

:00: D0 idle state, fetch frame buffer from 

system memory  

01: D0i1 not defined in VLVP 

02: D0i2 PSR is active, display controller is trunk gated 

03: D0i3 PSR is active, display controller is power gated

29:24

0b

RO

Reserved.

23:16

0b

RO

: Number of identical frames has been sent by display 

controller. Value is not roll over at 255.