Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Register Access Methods
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
67
Most message bus registers are located in the SoC Transaction Router. The default
opcode messages for those registers are as follows:
opcode messages for those registers are as follows:
•
Message ‘Read Register’ Opcode: 06h
•
Message ‘Write Register’ Opcode: 07h
Registers with different opcodes will be specified as applicable. Pseudo code of a
message bus register read is shown below (where ReadOp==0x06):
message bus register read is shown below (where ReadOp==0x06):
•
MyMCR[31:24] = ReadOp; MyMCR[23:16] = port; MyMCR[15:8] = offset;
•
MyMCR[7:4] = 0xf
•
PCIWRITE(0, 0, 0, 0xD0, MyMCR)
•
Register_Snapshot = PCIREAD(0, 0, 0, 0xD4)
3.7
Register Field Access Types
Port
23:16
Offset/Register
15:08
Byte Enable
07:04
Table 40. MCRX Description
Field
MBPER
Bits
Offset/Register Extension. This is used for messages sent to end points that
require more than 8 bits for the offset/register. These bits are a direct extension of
MCR[15:8].
require more than 8 bits for the offset/register. These bits are a direct extension of
MCR[15:8].
31:08
Table 39. MCR Description (Sheet 2 of 2)
Field
MBPR Bits
Table 41. Register Access Types and Definitions (Sheet 1 of 2)
Access Type
Meaning
Description
RO
Read Only
In some cases, if a register is read only, writes to this register location
have no effect. However, in other cases, two separate registers are located
at the same location where a read accesses one of the registers and a write
accesses the other register. See the I/O and memory map tables for
details.
have no effect. However, in other cases, two separate registers are located
at the same location where a read accesses one of the registers and a write
accesses the other register. See the I/O and memory map tables for
details.
WO
Write Only
In some cases, if a register is write only, reads to this register location
have no effect. However, in other cases, two separate registers are located
at the same location where a read accesses one of the registers and a write
accesses the other register. See the I/O and memory map tables for
details.
have no effect. However, in other cases, two separate registers are located
at the same location where a read accesses one of the registers and a write
accesses the other register. See the I/O and memory map tables for
details.
R/W
Read/Write
A register with this attribute can be read and written.