Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

825

LPE Audio Status

20:18

0b

RW

This field is used during read or write of different DIPs, 

and during read or write of ELD data. These bits are used as an index to their respective 

DIP or ELD buffers. When the index is not valid, the contents of the DIP will return all 0 

s. 

000 = (Default) Audio DIP (31 bytes of address space, 13 bytes of data)  

001 = Generic 1 (ACP) Data Island Packet (31 bytes of address space, 11 bytes of data) 

010 = Generic 2 (ISRC1) Data Island Packet (31 bytes of address space, 31 bytes of 

data) 

011 = Generic 3 (ISRC2) Data Island Packet (31 bytes of address space, 31 bytes of 

data) 

1XX = reserved

17:16

0b

RW

These bits reflect the frequency of DIP 

transmission for the DIP buffer type designated in bits 20:18. When writing DIP data, 

this value is also latched when the first DW of the DIP is written.When read, this value 

reflects the DIP transmission frequency for the DIP buffer designated in bits 20:18. 

00 = Disabled (Default) 

01 = once per frame 

10 = Send once  

11 = Best effort (Send at least every other vsync)

15

0b

RW

This R/W bit reflects the state of CP request from the audio unit. When an 

audio CP request has been serviced, it must be reset to 1 by the video software to 

indicate that the CP request has been serviced. 

0 = CP request pending or not ready to receive requests (default) 

1 = CP request ready 

CP_ready bit is programmable through Bit 14 for [DevCL, DevBLC]. 

CP_ready bit is programmable through Bit 15 for [DevCTG].  

Bit 15 Reserved for [DevCL, DevBLC].

14

0b

RW

ELD valid: This R/W bit reflects the state of the ELD data written to the 

ELD RAM. After writing the ELD data, the video software must set this bit to 1 to indicate 

that the ELD data is valid. At audio codec initialization, or on a hotplug event, this bit is 

set to 0 by the video software. This bit is reflected in the audio pin complex widget as 

the ELD valid status bit. 

0 = ELD data invalid (default, when writing ELD data, set 0 by software) 

1 = ELD data valid (Set by video software only) 

ELD bit is programmable through Bit 13 for [DevCL, DevBLC]. 

ELD bit is programmable through Bit 14 for [DevCTG].

13:9

0b

RW

ELD buffer size (read only)10000 = This field reflects the size of the ELD 

buffer in DWORDs 

13:9 reflects ELD buffer size for [DevCTG]. 

12:9 reflects ELD buffer size for [DevCL, DevBLC].

8:5

0b

RW

ELD access address (R/W): Selects the DWORD address for access to the 

ELD buffer (48 bytes). The value wraps back to zero when incremented past the max 

addressing value 0xF. This field change takes effect immediately after being written. The 

read value indicates the current access address.

4

0b

RW

ELD ACK: Acknowledgement from the audio driver that ELD read has 

been completed

3:0

0b

RW

Selects the DWORD address for access to the 

DIP buffers. The value wraps back to zero when it incremented past the max addressing 

value of 0xF. This field change takes effect immediately after being written. The read 

value indicates the current access address.