Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

924

Datasheet

Display B/Sprite Plane Control Register

31:12

0b

RW

This register provides the start address of the 

display B plane or the first eye when running in stereo mode. This address must be at 

least pixel aligned. This register can be written directly through software or by 

command packets in the command stream. It represents an offset from the graphics 

memory aperture base and is mapped to physical pages through the global GTT. 

This address must be 4K aligned. When performing asynchronous flips and the display 

surface is in tiled memory, this address must be 256K aligned. This register can be 

written directly through software or by command packets in the command stream. It 

represents an offset from the graphics memory aperture base and is mapped to physical 

pages through the global GTT. 

If the device supports trusted operation and this plane is not marked trusted, the 

memory pages must not be marked NoDMA .  

Write to this register triggers async flip The async flip address is written into the Display 

B Base Address register 0x7119C

11:4

0b

RW

Reserved.

3

0b

RW

Project: 

All 

 

Default Value: 

0b 

 

 

This bit indicates if the source of the flip is CS or BCS so display can send the flip done 

response to the appropriate destination.  

 

 

ValueNameDescriptionProject 

0b 

CS 

Flip source is CS 

All 

 

1b 

BCS 

Flip source is BCS 

All 

2

0b

RW

Project: 

All 

 

Default Value: 

0b 

 

 

This bit requests decryption to be enabled for this plane. This request will be qualified 

with the separate decryption allow message in order to create the decryption enable. 

This bit is only allowed to change on a synchronous flip, but once set with a synchronous 

flip, the bit can remain set while using asynchronous flips. This value is loaded into the 

surface base address register of the associated plane. Usage must conform to the rules 

outlined in the plane surface base address register.  

1:0

0b

RW

Reserved.