LSI 53C875A User Manual
Load and Store Instructions
5-35
5.7.4 Third Dword
TEMP Register
[31:0]
These bits contain the destination address for the
Memory Move.
Memory Move.
5.8 Load and Store Instructions
The Load and Store instructions provide a more efficient way to move
data from/to memory to/from an internal register in the chip without using
the normal memory move instruction.
data from/to memory to/from an internal register in the chip without using
the normal memory move instruction.
The Load and Store instructions are represented by two Dword opcodes.
The first Dword contains the
The first Dword contains the
and
register values. The second Dword contains the
value. This is either the actual memory
location of where to Load and Store, or the offset from the
, depending on the value of bit 28 (DSA Relative).
A maximum of 4 bytes may be moved with these instructions. The
register address and memory address must have the same byte
alignment, and the count set such that it does not cross Dword
boundaries. The memory address may not map back to the chip,
excluding RAM and ROM. If it does, a PCI read/write cycle occurs (the
data does not actually transfer to/from the chip), and the chip issues an
interrupt (Illegal Instruction Detected) immediately following.
register address and memory address must have the same byte
alignment, and the count set such that it does not cross Dword
boundaries. The memory address may not map back to the chip,
excluding RAM and ROM. If it does, a PCI read/write cycle occurs (the
data does not actually transfer to/from the chip), and the chip issues an
interrupt (Illegal Instruction Detected) immediately following.
31
0
Register
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit A1
Bit A0
Number of Bytes Allowed to Load and Store
0
0
One, two, three or four
0
1
One, two, or three
1
0
One or two
1
1
One