LSI 53C875A User Manual
5-36
SCSI SCRIPTS Instruction Set
The SIOM and DIOM bits in the
register determine
whether the destination or source address of the instruction is in Memory
space or I/O space, as illustrated in the following table. The Load and
Store utilizes the PCI commands for I/O read and I/O write to access the
I/O space.
space or I/O space, as illustrated in the following table. The Load and
Store utilizes the PCI commands for I/O read and I/O write to access the
I/O space.
5.8.1 First Dword
IT[2:0]
Instruction Type
[31:29]
These bits should be 0b111, indicating the Load and
Store instruction.
Store instruction.
DSA
DSA Relative
28
When this bit is cleared, the value in the
is the actual 32-bit memory address
used to perform the Load and Store to/from. When this
bit is set, the chip determines the memory address to
perform the Load and Store to/from by adding the 24-bit
signed offset value in the
bit is set, the chip determines the memory address to
perform the Load and Store to/from by adding the 24-bit
signed offset value in the
to the
.
R
Reserved
[27:26]
NF
No Flush (Store instruction only)
25
When this bit is set, the LSI53C875A performs a Store
without flushing the prefetch unit. When this bit is cleared,
the Store instruction automatically flushes the prefetch
unit. Use No Flush if the source and destination are not
within four instructions of the current Store instruction.
This bit has no effect on the Load instruction.
without flushing the prefetch unit. When this bit is cleared,
the Store instruction automatically flushes the prefetch
unit. Use No Flush if the source and destination are not
within four instructions of the current Store instruction.
This bit has no effect on the Load instruction.
Bit
Source
Destination
SIOM (Load)
Memory
Register
DIOM (Store)
Register
Memory
31
29
28
27 26 25 24 23 22
16 15
3
2
0
Register
Register
IT[2:0]
DSA
R
NF LS R
RA[6:0]
R
BC
1
1
1
x
0
0
x
x
0
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x