Atmel SpaceWire Router SpW-10X User Manual
Ref.: UoD_SpW-10X_
UserManual
Issue: 3.4
SpW-10X
SpaceWire Router
User Manual
Date: 11
th
July 2008
Preliminary
43
Table 5-6 Reset Configuration Signals
Signal Dir
Description
Signal
Type
STAT_MUX_OUT(2:0)
[maps to -> POR_TX_RATE(2:0)]
In
Sets the transmitter maximum data rate after
reset. The data rate can subsequently be
changed during normal operation using port
configuration commands. The values are
listed below.
“111” – Full data rate after link start-up.
“110” – 1/2 data rate after link start-up.
“101” – 1/3 data rate after link start-up.
“100” – 1/4 data rate after link start-up.
“011” – 1/5 data rate after link start-up.
“010” – 1/6 data rate after link start-up.
“001” – 1/7 data rate after link start-up.
“000” – 1/8 data rate after link start-up.
Note: POR_TX_RATE affects all SpaceWire
ports in the router.
Note: The data rate is dependent on
reset. The data rate can subsequently be
changed during normal operation using port
configuration commands. The values are
listed below.
“111” – Full data rate after link start-up.
“110” – 1/2 data rate after link start-up.
“101” – 1/3 data rate after link start-up.
“100” – 1/4 data rate after link start-up.
“011” – 1/5 data rate after link start-up.
“010” – 1/6 data rate after link start-up.
“001” – 1/7 data rate after link start-up.
“000” – 1/8 data rate after link start-up.
Note: POR_TX_RATE affects all SpaceWire
ports in the router.
Note: The data rate is dependent on
FEEDBDIV
at reset
CMOS3V3
STAT_MUX_OUT(3)
[maps to ->
POR_ADDR_SELF_N
In
If asserted (low) after reset allows a router
port to address itself and therefore cause an
input packet to be returned through the same
input port. This mode may only be suitable for
debug and test operations.
This signal is active low.
port to address itself and therefore cause an
input packet to be returned through the same
input port. This mode may only be suitable for
debug and test operations.
This signal is active low.
CMOS3V3
STAT_MUX_OUT(4)
[maps to ->
POR_TIMEOUT_EN_N]
In
Power on reset signal which determines if
output port timeouts are enabled at start-up.
When asserted (low) the port timeouts are
enabled. When de-asserted (high) they are
disabled.
This signal is active low.
An external pull down resistor (e.g. 4k7
output port timeouts are enabled at start-up.
When asserted (low) the port timeouts are
enabled. When de-asserted (high) they are
disabled.
This signal is active low.
An external pull down resistor (e.g. 4k7
Ω) is
recommended on this pin so to enable the
watchdog timers.
watchdog timers.
CMOS3V3
STAT_MUX_OUT(5)
[maps to ->
POR_SEL_TIMEOUT0_N]
In
Power on reset value which determines the
initial timeout value. The following values
determine which timeout is selected at power
initial timeout value. The following values
determine which timeout is selected at power
CMOS3V3