Delta Tau GEO BRICK LV Reference Manual
Turbo PMAC/PMAC2 Software Reference
Turbo PMAC Global I-Variables
201
I6805, I6855, I6905, and I6955 control the DAC strobe signal for the two supplemental machine interface
channels of MACRO ICs 0, 1, 2, and 3, respectively, provided they are DSPGATE2 ICs.
channels of MACRO ICs 0, 1, 2, and 3, respectively, provided they are DSPGATE2 ICs.
The 24-bit word set by this variable for the IC is shifted out serially on the DAC_STROB lines, MSB
first, one bit per DAC_CLK cycle starting on the rising edge of the phase clock. The value in the LSB is
held until the next phase clock cycle.
first, one bit per DAC_CLK cycle starting on the rising edge of the phase clock. The value in the LSB is
held until the next phase clock cycle.
For typical n-bit DACs, the strobe line is held high for n-1 clock cycles. Therefore, the common settings
of this variable are:
of this variable are:
18-bit DACs: $7FFFC0 (high for 17 clock cycles)
16-bit DACs: $7FFF00 (high for 15 clock cycles)
12-bit DACs: $7FF000 (high for 11 clock cycles)
Note:
By default, the DAC circuitry of a MACRO IC is not used on a Turbo PMAC2.
The DAC lines are the alternate use of lines on the I/O port.
The DAC lines are the alternate use of lines on the I/O port.
I6806/I6856/I6906/I6956 MACRO IC ADC Strobe Word
Range:
$000000 - $FFFFFF
Units:
Serial Data Stream (MSB first, starting on rising edge of phase clock)
Default:
$FFFFFE
Note:
This I-variable is only active if the MACRO IC is present, and is a DSPGATE2 IC.
The presence and type of MACRO ICs are reported in I4902 and I4903.
The presence and type of MACRO ICs are reported in I4902 and I4903.
I6806, I6856, I6906, and I6956 control the ADC strobe signal for the two supplemental machine interface
channels of MACRO ICs 0, 1, 2, and 3, respectively, provided they are DSPGATE2 ICs. The 24-bit
word set by this variable for the IC is shifted out serially on the ADC_STROB lines, MSB first, one bit
per DAC_CLK cycle starting on the rising edge of the phase clock. The value in the LSB is held until the
next phase clock cycle.
channels of MACRO ICs 0, 1, 2, and 3, respectively, provided they are DSPGATE2 ICs. The 24-bit
word set by this variable for the IC is shifted out serially on the ADC_STROB lines, MSB first, one bit
per DAC_CLK cycle starting on the rising edge of the phase clock. The value in the LSB is held until the
next phase clock cycle.
The first 1 creates a rising edge on the ADC_STROB output that is used as a start-convert signal. Some
A/D converters just need this rising edge for the conversion; others need the signal to stay high all of the
way through the conversion. The LSB of I6806 should always be set to 0 so that a rising edge is created
on the next cycle. The default I6806 value of $FFFFFE is suitable for virtually all A/D converters.
A/D converters just need this rising edge for the conversion; others need the signal to stay high all of the
way through the conversion. The LSB of I6806 should always be set to 0 so that a rising edge is created
on the next cycle. The default I6806 value of $FFFFFE is suitable for virtually all A/D converters.
The A/D converters used on matching Delta Tau products just need the rising edge at the start of a
conversion cycle; this permits intermediate bits in the data stream to be used as special control bits. Delta
Tau’s Acc-8T Supplemental Flag Multiplexer Board uses these bits to control the multiplexing; Delta
Tau’s Acc-8K1 Fanuc C/S-Series PWM Interface Board uses these bits to control the magnetic contactors
on the drives.
conversion cycle; this permits intermediate bits in the data stream to be used as special control bits. Delta
Tau’s Acc-8T Supplemental Flag Multiplexer Board uses these bits to control the multiplexing; Delta
Tau’s Acc-8K1 Fanuc C/S-Series PWM Interface Board uses these bits to control the magnetic contactors
on the drives.
Note:
By default, the ADC circuitry on a MACRO IC is not used on a Turbo PMAC2.
The ADC lines are the alternate use of pins on the Multiplexer port.
The ADC lines are the alternate use of pins on the Multiplexer port.
I6807/I6857/I6907/I6957 MACRO IC Clock Direction Control
Range:
0 – 3 (DSPGATE2 IC); 0 – 1 (MACROGATE IC)
Units:
none
Default:
System dependent
I6807, I6857, I6907, and I6957 control whether MACRO ICs 0, 1, 2, and 3, respectively, use their own
internally generated servo and phase clock signals, or whether they use servo and phase clock signals
from a source external to them (usually MACRO IC 0 or Servo IC 0).
internally generated servo and phase clock signals, or whether they use servo and phase clock signals
from a source external to them (usually MACRO IC 0 or Servo IC 0).