Delta Tau GEO BRICK LV Reference Manual
Turbo PMAC/PMAC2 Software Reference
Turbo PMAC Global I-Variables
224
When I7mn4 is set to 0, the encoder index channel input (CHCn) is passed directly into the position
capture circuitry.
capture circuitry.
When I7mn4 is set to 1, the encoder index channel input (CHCn) is logically combined with (gated by)
the quadrature signals of Encoder n before going to the position capture circuitry. The intent is to get a
gated index signal exactly one quadrature state wide. This provides a more accurate and repeatable
capture, and makes the use of the capture function to confirm the proper number of counts per revolution
very straightforward.
the quadrature signals of Encoder n before going to the position capture circuitry. The intent is to get a
gated index signal exactly one quadrature state wide. This provides a more accurate and repeatable
capture, and makes the use of the capture function to confirm the proper number of counts per revolution
very straightforward.
In order for the gated index capture to work reliably, the index pulse must reliably span one, but only one,
high-high or low-low AB quadrature state of the encoder. I7mn5 allows the selection of which of these
two possibilities is used.
high-high or low-low AB quadrature state of the encoder. I7mn5 allows the selection of which of these
two possibilities is used.
Note:
If I7mn4 is set to 1, but I7mn2 bit 0 is set to 0, so the index is not used in the
position capture, then the encoder position is captured on the first edge of any of
the U, V, or W flag inputs for the channel. In this case, bits 0, 1, and 2 of the
channel status word tell what hall-state edge caused the capture.
position capture, then the encoder position is captured on the first edge of any of
the U, V, or W flag inputs for the channel. In this case, bits 0, 1, and 2 of the
channel status word tell what hall-state edge caused the capture.
I7mn5
Servo IC m Channel n Encoder Index Gate State/Demux Control
Range:
0 - 3
Units:
none
Default:
0
I7mn5 is a 2-bit variable that controls two functions for the index channel of the encoder.
When using the gated index feature of a PMAC2-style Servo IC for more accurate position capture
(I7mn4=1), bit 0 of I7mn5 specifies whether the raw index-channel signal fed into Encoder n of Servo IC
m is passed through to the position capture signal only on the high-high quadrature state (bit 0 = 0), or
only on the low-low quadrature state (bit 0 = 1).
(I7mn4=1), bit 0 of I7mn5 specifies whether the raw index-channel signal fed into Encoder n of Servo IC
m is passed through to the position capture signal only on the high-high quadrature state (bit 0 = 0), or
only on the low-low quadrature state (bit 0 = 1).
Bit 1 of I7mn5 controls whether the Servo IC de-multiplexes the index pulse and the three hall-style
commutation states from the third channel based on the quadrature state, as with Yaskawa incremental
encoders. If bit 1 is set to 0, this de-multiplexing function is not performed, and the signal on the C
channel of the encoder is used as the index only. If bit 1 is set to 1, the Servo IC breaks out the third-
channel signal into four separate values, one for each of the four possible AB-quadrature states. The de-
multiplexed hall commutation states can be used to provide power-on phase position using Ixx81 and
Ixx91.
commutation states from the third channel based on the quadrature state, as with Yaskawa incremental
encoders. If bit 1 is set to 0, this de-multiplexing function is not performed, and the signal on the C
channel of the encoder is used as the index only. If bit 1 is set to 1, the Servo IC breaks out the third-
channel signal into four separate values, one for each of the four possible AB-quadrature states. The de-
multiplexed hall commutation states can be used to provide power-on phase position using Ixx81 and
Ixx91.
The following table shows what hall or index state is broken out for each of the four quadrature states:
A
B
C
1
1
Z
1
0
U
0
0
V
0
1
W
Note:
The B revision or newer of the DSPGATE1 Servo IC is required to support this
hall de-multiplexing feature.
hall de-multiplexing feature.