Delta Tau GEO BRICK LV User Manual

Boards With Switch-Set Addresses 

For the Acc-14E, 65E, 66E, and 67E boards, the base address of the board is determined by the settings of 
DIP switches SW1-1 through SW1-4.  When these boards are used with a UMAC Turbo CPU, SW1-5 
and SW1-6 must always be ON.  These boards always appear in the low byte (bits 0 – 7) of the 24-bit 
word. 

SW1-1 ON 
SW1-2 ON 

Y:$078C00 Y:$079C00 Y:$07AC00 Y:$07BC00 

SW1-1 OFF 

SW1-2 ON 

Y:$078D00 Y:$079D00 Y:$07AD00 Y:$07BD00 

SW1-1 ON 

SW1-2 OFF 

Y:$078E00 Y:$079E00 Y:$07AE00 Y:$07BE00 

SW1-1 OFF 
SW1-2 OFF 

Y:$078F00 Y:$079F00 Y:$07AF00 Y:$07BF00 

Note that both types of boards can be set up to the same addresses in some cases.  It is, of course, very 
important not to have any addressing conflicts. 

I/O points on the IOGATE IC itself are selectable by byte for input or output.  However, only the Acc-
14E TTL-level I/O board gives you a choice as to which I/O points will be inputs and which will be 
outputs.  On all the other of these boards, the surrounding buffer/driver circuitry determines how each I/O 
point must be used.  The IOGATE IC must be set up each power-on/reset to determine the direction of 
each I/O point; typically this is done in a “one-shot” PLC program.  The manual for each board shows 
example program code that could be used to do this. 

In typical applications, very little setup of the IOGATE IC is required for operation with the UMAC I/O 
boards.  However, the IOGATE IC has special features that are useful in unusual applications.  The 
following section details how the control register and the setup registers of the IOGATE IC can be used to 
provide great flexibility 

Control Register 

The control register at address {Base + 7} permits the configuration of the IOGATE IC to a variety of 
applications.  The control register consists of 8 write/read-back bits – Bits 0 - 7. 

Direction Control Bits 
Bits 0 to 5 of the control register simply control the direction of the I/O for the matching numbered data 
register.  That is, Bit n controls the direction of the I/O at {Base + n}.  A value of 0 in the control bit (the 
default) permits a write operation to the data register, enabling the output function for each line in the 
register.  Enabling the output function does not prevent the use of any or all of the lines as inputs, as long 
as the outputs are off (non-conducting).  A value of 1 in the control bit does not permit a write operation 
to the data register, disabling the output, reserving the register for inputs.   

For example, a value of 1 in Bit 3 disables the write function into the data register at address {Base + 3}, 
ensuring that lines IO24 - IO31 can always be used as inputs. 

Register Select Control Bits 
Bits 6 and 7 of the control register together select which of 4 possible registers can be accessed at each of 
the addresses {Base + 0} through {Base + 5}.  They also select which of two possible registers can be 
selected at {Base + 6}.