Delta Tau GEO BRICK LV User Manual
Turbo PMAC User Manual
204
Turbo PMAC General Purpose I/O Use
The following table explains how these bits select registers:
Bit 7
Bit 6
Combined
Value
Byte
Value*
{Base + 0} to {Base + 5}
Register Selected
{Base + 6} Register
Selected
0
0
0
$00
Data Register
Data Register
0
1
1
$40
Setup Register 1
Setup Register
1 0
2
$80
Setup
Register
2
1
1
3
$C0
Setup Register 3
n. a.
* With bits 0 to 5 set to 0
In a typical application, non-zero combined values of Bits 6 and 7 are only used for initial configuration
of the IC. These values are used to access the setup registers at the other addresses. After the
configuration is finished, zeros are written to both Bits 6 and 7, so the data registers at the other registers
can be accessed.
of the IC. These values are used to access the setup registers at the other addresses. After the
configuration is finished, zeros are written to both Bits 6 and 7, so the data registers at the other registers
can be accessed.
Setup Registers
There are a total of four registers accessible at each of the IC addresses {Base + 0} to {Base + 5}: three 8-
bit setup registers and an 8-bit data register. The setup registers control how data is written to and read
from the data registers.
bit setup registers and an 8-bit data register. The setup registers control how data is written to and read
from the data registers.
Setup Register 1: Inversion Control
Setup Register 1 at each address {Base + 0} through {Base + 5}, which is selected by writing a 1 to Bit 6
of the Control Word at {Base + 7} and a 0 to Bit 7, is the inversion control register for the Data Register
at the same address. Each bit of Setup Register 1 controls the inversion of the matching bit of the Data
Register at the same address.
Setup Register 1 at each address {Base + 0} through {Base + 5}, which is selected by writing a 1 to Bit 6
of the Control Word at {Base + 7} and a 0 to Bit 7, is the inversion control register for the Data Register
at the same address. Each bit of Setup Register 1 controls the inversion of the matching bit of the Data
Register at the same address.
A value of 0 in a bit of Setup Register 1 specifies an inverting I/O point for the matching bit of the Data
Register at the same address. That is, for an output, a value of 0 produces a low (conducting) output, and
a value of 1 produces a high (non-conducting) output. For an input, a line pulled low produces a 1 value,
and a line pulled high or permitted to float high produces a 0 value.
Register at the same address. That is, for an output, a value of 0 produces a low (conducting) output, and
a value of 1 produces a high (non-conducting) output. For an input, a line pulled low produces a 1 value,
and a line pulled high or permitted to float high produces a 0 value.
A value of 1 in a bit of Setup Register 1 specifies a non-inverting I/O point for the matching bit of the
Data Register at the same address. That is, for an output, a value of 0 produces a high (non-conducting)
output, and a value of 1 produces a low (conducting) output. For an input, a line pulled low produces a 0
value, and a line pulled high or permitted to float high produces a 1 value.
Data Register at the same address. That is, for an output, a value of 0 produces a high (non-conducting)
output, and a value of 1 produces a low (conducting) output. For an input, a line pulled low produces a 0
value, and a line pulled high or permitted to float high produces a 1 value.
Setup Register 2: Read Control
Setup Register 2 at each address {Base + 0} through {Base + 5}, which is selected by writing a 0 to Bit 6
of the Control Word at {Base + 7} and a 1 to Bit 7, is the read control register for the Data Register at the
same address. Each bit of Setup Register 2 controls what data is read from the matching bit of the Data
Register at the same address.
Setup Register 2 at each address {Base + 0} through {Base + 5}, which is selected by writing a 0 to Bit 6
of the Control Word at {Base + 7} and a 1 to Bit 7, is the read control register for the Data Register at the
same address. Each bit of Setup Register 2 controls what data is read from the matching bit of the Data
Register at the same address.
The action of a bit of Setup Register 2 is dependent on the setting of the matching bit of Setup Register 3
for the same address. If the matching bit of Setup Register 3 is 0, selecting unlatched inputs, the bit of
Setup Register 2 controls whether the pin value is read, or the value in the writeable register is read. A
value of 0 in the bit of Setup Register 2 selects the pin value to be read from the matching bit of the Data
Register at the same address; a value of 1 in the bit selects the writeable register value.
for the same address. If the matching bit of Setup Register 3 is 0, selecting unlatched inputs, the bit of
Setup Register 2 controls whether the pin value is read, or the value in the writeable register is read. A
value of 0 in the bit of Setup Register 2 selects the pin value to be read from the matching bit of the Data
Register at the same address; a value of 1 in the bit selects the writeable register value.
If the matching bit of Setup Register 3 is 1, selecting latched inputs, the bit of Setup Register 2 controls
whether the directly latched data is read, or the value that is the result of a Gray-code-to-binary
conversion. A value of 0 in the bit of Setup Register 2 selects the directly latched value to be read from
the matching bit of the Data Register at the same address; a value of 1 in the bit selects the value that is
the result of a Gray-code-to-binary conversion.
whether the directly latched data is read, or the value that is the result of a Gray-code-to-binary
conversion. A value of 0 in the bit of Setup Register 2 selects the directly latched value to be read from
the matching bit of the Data Register at the same address; a value of 1 in the bit selects the value that is
the result of a Gray-code-to-binary conversion.