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Turbo PMAC User Manual 
406 
Writing a Host Communications Program 
2.  Write the control character to Bits 0 – 7 of 0x0E9E (X:$0603A7). 
3.  Each background cycle, Turbo PMAC will read this byte.  If the byte contains a non-zero value, 
Turbo PMAC will take the appropriate action for the command, and set the byte back to 0. 
Reading a Response Line: To read an ASCII response line from the Turbo PMAC through the DPRAM: 
1.  Wait for the Host-Input Control Word at 0x0F40 (Y:$063D0) to become greater than 0, indicating 
that a response line is ready. 
2.  Interpret the value in this register to determine what type of response is present.  If Bit 15 is 1, Turbo 
PMAC is reporting an error in the command, and there is no response other than this word.  In this 
case, Bits 0 – 11 encode the error number for the command as 3 BCD digits.  
 
If Bit 15 is 0, there is no error, and there is a response string.  Bits 8 and 9 tell what caused the 
response.  If they form a value of 0, a command from the host computer caused the response.  If they 
form a value of 1, an internal CMDR statement caused the response.  If they form a value of 2, an 
internal SENDR statement caused the response.  Note the value in Bits 0 – 7.  These will determine 
whether this is the last line in the response or not (see Step 5, below). 
3.  Read the response string starting at 0x0F44 (Y:$0603D1). Two 8-bit characters are packed into each 
16-bit word; the first character is placed into the low byte.  Subsequent characters are placed into 
consecutive higher addresses, two per 16-bit word.  (In byte addressing, each character is read from 
an address one higher than the preceding character.)  Up to 255 characters can be sent in a single 
response line. The string is terminated with the NULL character (byte value 0), convenient for C-style 
string handling.  For Pascal-style string handling, the register at 0x0F42 (X:$0603D0) contains the 
number of characters in the string (plus one). 
4.  Clear the Host-Input Control Word at 0x0F40 (Y:$063D0) to 0.  Turbo PMAC will not send another 
response line until it sees this register set to 0. 
5.  If Bits 0 – 7 of the Host-Input Control Word had contained the value $0D (13 decimal, “CR”), this 
was not the last line in the response, and steps 1 – 4 should be repeated.  If they had contained the 
value $06 (6 decimal, “ACK”), this was the last line in the response. 
Note that the communications routines of the PCOMM32 library do all of these actions automatically.  If 
writing a custom low-level communications routine, this operation is fundamentally a string copy operation. 
DPRAM Communications Interrupts 
If I56 is set to 1, Turbo PMAC will interrupt the host computer whenever it has a response line ready for 
the host to read.  This interrupt has the potential to make the host communications more efficient, because 
the computer does not need to poll the DPRAM to see when a response is ready. 
VME Interrupt: On any of the VME-bus Turbo PMACs, this interrupt will appear on the VME-bus 
interrupt line specified by I95.  It will have an interrupt vector equal to (I96 + 1). 
ISA Interrupt: On the ISA-bus Turbo PMACs, this interrupt will appear on the ISA-bus interrupt line 
(IRQn) selected by an E-point jumper on the board.  The interrupt controller IC on the board can pass 
interrupts from eight different sources (IR0 – IR7) through this interrupt line.   
On a Turbo PMAC-PC, source IR7 is used to generate the interrupt.  Jumper E85 must be ON, and 
jumpers E82 – E84 must be OFF for this feature to work.  This brings the EQU4 line (position compare 
for encoder 4) into the interrupt controller – the position-compare function for this encoder may not be 
used for other purposes in this case. 
On a Turbo PMAC2-PC, source IR5 is used to generate the interrupt from the EQU1 line (position 
compare for Encoder 1).  The position-compare function for this encoder may not be used for other 
purposes in this case. 
On a Turbo PMAC2-PC Ultralite, source IR5 is used to generate the interrupt from the CTRL0 line of the 
DSPGATE2 IC, which does not have other functions.