Delta Tau GEO BRICK LV User Manual
Turbo PMAC User Manual
Writing a Host Communications Program
407
Turbo PMAC will continue to assert this interrupt source until the host has cleared the Host-Interrupt
Control Word. Because of this, the host may see the source still active when it gets an interrupt from
another source.
Control Word. Because of this, the host may see the source still active when it gets an interrupt from
another source.
DPRAM Background Variable Read Buffer
The Background Variable Data Read Buffer permits you to have up to 128 user-specified Turbo PMAC
registers copied into DPRAM during the background cycle. This function is controlled by I55. The
buffer has two modes of operation, single-user and multi-user. The default mode is single-user. It is
active when bit 8 of the control word 0x1044 (Y:$060411) is set to zero. Multi-user mode is active when
bit 8 of the control word is set to one.
General Description: The buffer has three parts. The first part is the header: 4 16-bit words (8 host
addresses) containing handshake information and defining the location and size of the rest of the table.
This is at a fixed location in DPRAM (see table below).
The second part contains the address specifications of the Turbo PMAC registers to be copied into
DPRAM. It occupies two 16-bit words (four host addresses) for each Turbo PMAC location to be copied,
starting at the location specified in the header.
The third part, starting immediately after the end of the second part, contains the copied information from
the Turbo PMAC registers. It contains 2 16-bit words (four host addresses) for each short (X or Y) Turbo
PMAC location copied, and four 16-bit words (eight host addresses) for each long Turbo PMAC location
copied. The data format is the same as for data gathering to dual-ported RAM.
Register Map
registers copied into DPRAM during the background cycle. This function is controlled by I55. The
buffer has two modes of operation, single-user and multi-user. The default mode is single-user. It is
active when bit 8 of the control word 0x1044 (Y:$060411) is set to zero. Multi-user mode is active when
bit 8 of the control word is set to one.
General Description: The buffer has three parts. The first part is the header: 4 16-bit words (8 host
addresses) containing handshake information and defining the location and size of the rest of the table.
This is at a fixed location in DPRAM (see table below).
The second part contains the address specifications of the Turbo PMAC registers to be copied into
DPRAM. It occupies two 16-bit words (four host addresses) for each Turbo PMAC location to be copied,
starting at the location specified in the header.
The third part, starting immediately after the end of the second part, contains the copied information from
the Turbo PMAC registers. It contains 2 16-bit words (four host addresses) for each short (X or Y) Turbo
PMAC location copied, and four 16-bit words (eight host addresses) for each long Turbo PMAC location
copied. The data format is the same as for data gathering to dual-ported RAM.
Register Map
Background Variable Read Buffer Part 1
Definition and Basic Handshaking
Address Description
0x1044
(Y:$060411)
(Y:$060411)
PMAC to Host (Bit 0 = 1 for single user mode) Data Ready. PMAC
done updating buffer - Host must clear for more data.
done updating buffer - Host must clear for more data.
0x1046
(X:$060411)
(X:$060411)
Servo Timer (Updated at Data Ready Time)
0x1048
(Y:$060412)
(Y:$060412)
Size of Data Buffer (measured in long integers of 32 bits each)
0x104A
(X:$060412)
(X:$060412)
Starting Turbo PMAC Offset of Data Buffer from beginning of
variable-buffer space $060450 (e.g.. $0100 for starting PMAC
address $060550 – host address offset 0x1540)
variable-buffer space $060450 (e.g.. $0100 for starting PMAC
address $060550 – host address offset 0x1540)
Background Variable Read Buffer Part 2
Variable Address Buffer Format (2x16-bit words)
X:Mem
Bits 15: Data Ready
(multi-user mode)
Bits 15: Data Ready
(multi-user mode)
X:Mem
Bits 4 – 5: Variable
type to read
Bits 0 – 3: Bits 16 – 19
of address
Bits 4 – 5: Variable
type to read
Bits 0 – 3: Bits 16 – 19
of address
Y:Mem
Bits 0 – 15 of PMAC
address of register to
read
Bits 0 – 15 of PMAC
address of register to
read
Dual
Port
Data
Length
Port
Data
Length
1 = PMAC data ready
0 = Host request data
0 = Host request data
Bits 4 – 5 = 0: PMAC
Var. Y:Mem.
Var. Y:Mem.
PMAC Address of Variable
32 bits
1 = PMAC data ready
0 = Host request data
0 = Host request data
Bits 4 – 5 = 1: PMAC
Var. Long
Var. Long
PMAC Address of Variable
64 bits
1 = PMAC data ready
0 = Host request data
0 = Host request data
Bits 4 – 5 = 2: PMAC
Var. X:Mem.
Var. X:Mem.
PMAC Address of Variable
32 bits