Delta Tau GEO BRICK LV User Manual
Turbo PMAC User Manual
Writing a Host Communications Program
409
When the host wants to read a register, it should check to see that Bit 15 of the data type specifier (the
Data Ready bit) has been set. If it has, the host can begin reading and processing the data from that
register. When it is done, it should clear the Data Ready bit to let Turbo PMAC know that it can update
that register the next cycle.
Data Ready bit) has been set. If it has, the host can begin reading and processing the data from that
register. When it is done, it should clear the Data Ready bit to let Turbo PMAC know that it can update
that register the next cycle.
Data Format: Each 24-bit (X or Y) register is sign-extended to 32 bits. For a 48-bit (Long) register, each
24-bit half is sign-extended to 32 bits, for a total of 64 bits in the DPRAM. This data starts immediately
after the last address specification register.
24-bit half is sign-extended to 32 bits, for a total of 64 bits in the DPRAM. This data starts immediately
after the last address specification register.
Disabling: To disable this function, you can set the size register 0x1048 (Y:$060412) to 0, or simply
leave the individual Data Ready bit(s) set.
leave the individual Data Ready bit(s) set.
DPRAM Background Variable Data Write Buffer
The Background Variable Data Write Buffer is essentially the opposite of the Background Variable Data
Read Buffer described above. It lets you write to up to 32 user-specified registers or particular bits in
registers to Turbo PMAC without using a communications port (PCbus, serial, or DPRAM ASCII I/O).
This lets you set any Turbo PMAC variable without using an ASCII command such as M1=1 and without
worrying about an open Rotary Buffer. This function is controlled by I55.
Read Buffer described above. It lets you write to up to 32 user-specified registers or particular bits in
registers to Turbo PMAC without using a communications port (PCbus, serial, or DPRAM ASCII I/O).
This lets you set any Turbo PMAC variable without using an ASCII command such as M1=1 and without
worrying about an open Rotary Buffer. This function is controlled by I55.
General Description: The buffer has two parts. The first part is the header: 2 16-bit words (4 host
addresses) containing handshake information and defining the location and size of the rest of the table.
This is at a fixed location in DPRAM (Turbo PMAC address $060413 as shown in the table below).
addresses) containing handshake information and defining the location and size of the rest of the table.
This is at a fixed location in DPRAM (Turbo PMAC address $060413 as shown in the table below).
The second part contains the address specifications of the Turbo PMAC registers to be copied into Turbo
PMAC. It occupies 6 x 16-bit words (12 host addresses) for each Turbo PMAC location to be written to,
starting at the location specified in the header.
PMAC. It occupies 6 x 16-bit words (12 host addresses) for each Turbo PMAC location to be written to,
starting at the location specified in the header.
Registers:
Background Variable Data Write Buffer Part 1
Definition and Basic Handshaking
Address Description
0x104C
(Y:$060413)
HOST to PMAC Data Transferred. PMAC is updated when cleared.
Host must set for another update.
Host must set for another update.
0x07E8
(X:$060413)
Starting Turbo PMAC Offset of Data Buffer from beginning of
variable-buffer space $060450 (e.g.. $0100 for starting PMAC
address $060550 – host address offset 0x1540)
variable-buffer space $060450 (e.g.. $0100 for starting PMAC
address $060550 – host address offset 0x1540)
Background Variable Write Buffer Part 2
Format for each Data Structure (6x16-bit)
Address
X-Register Contents
Y-Register Contents
n
Bits 11 – 15: Offset (= 0 – 23) – Starting bit
number of target register into which value will be
written
Bits 6 – 10: Width (= 0, 1, 4, 8, 12, 16, or 20 – 0
represent 24 bits) – number of bits of target
register into which value will be written
Bits 3 – 5: Type of target register
=0: Y-register
= 1: Long (X/Y-register)
= 2: X-register
Bits 0 – 2: Upper 3 bits (bits 16 – 18) of target
register address
number of target register into which value will be
written
Bits 6 – 10: Width (= 0, 1, 4, 8, 12, 16, or 20 – 0
represent 24 bits) – number of bits of target
register into which value will be written
Bits 3 – 5: Type of target register
=0: Y-register
= 1: Long (X/Y-register)
= 2: X-register
Bits 0 – 2: Upper 3 bits (bits 16 – 18) of target
register address
Bits 0 – 15 of target register
address
n+1
Upper 16 bits of data word 1
Lower 16 bits of data word 1
n+2
Upper 16 bits of data word 2 (only used for writing
into long register)
into long register)
Lower 16 bits of data word 2
(only used for writing into long
register)
(only used for writing into long
register)