Delta Tau GEO BRICK LV User Manual
Turbo PMAC User Manual
80
Basic Motor Setup
PMAC2 Pulse and Direction Stepper System
Over/Under flow
Pulse
Stepper
Drive
Direction
Accumulator
Adder
PID
E
Decoder/
Counter
PMAC2
Drive and Motor
Master
Position
Trajectory
Generation
-
+
+
PFM Circuit
Note:
The analog output of a PMAC-style Servo IC, used in sign-and-magnitude mode
(Ixx96=1), and passed through a voltage-to-frequency converter, can be used for
the same type of operation. However, it is strongly recommended that the purely
digital method of the PMAC2-style Servo IC be used instead.
(Ixx96=1), and passed through a voltage-to-frequency converter, can be used for
the same type of operation. However, it is strongly recommended that the purely
digital method of the PMAC2-style Servo IC be used instead.
Hardware Setup
PMAC2-style Servo ICs, and the DSPGATE2 MACRO IC, have pulse-and-direction outputs for each
channel on the IC. In most configurations of interface and breakout hardware, these signals are accessible
as RS-422-level differential line-driver output pairs. These signals are driven by the value in output
register C for the channel, with the pulse frequency proportional to the value in this register. For this
reason, these outputs are technically known as pulse-frequency-modulated (PFM) outputs.
Alternately, the signals from the C output register can be used as pulse-width-modulated (PWM) outputs,
and commonly form the third-phase command signals for direct-PWM output of brushless motors. Note
that if using the channel for direct-PWM control of a motor, the PFM outputs will not be seen on the same
channel.
For board-level Turbo PMAC2 controllers and 3U-format stack boards (Acc-1E and 2E), the Acc-8S
breakout board usually is the most effective way of bringing out the pulse-and-direction signals. These
signals are available also on the Acc-8A and Acc-8E analog breakout boards and the Acc-8F PWM
breakout boards (as the third-phase PWM).
The pulse-and-direction signals are available on the encoder connectors of the QMAC boxed controller
and of the UMAC Acc-24E2S, Acc-24E2A, and Acc-24E2 axis-interface boards. The outputs use the
same pins as the T, U, V, and W flag inputs for the channel; a jumper must be installed to enable the
outputs on these pins.
channel on the IC. In most configurations of interface and breakout hardware, these signals are accessible
as RS-422-level differential line-driver output pairs. These signals are driven by the value in output
register C for the channel, with the pulse frequency proportional to the value in this register. For this
reason, these outputs are technically known as pulse-frequency-modulated (PFM) outputs.
Alternately, the signals from the C output register can be used as pulse-width-modulated (PWM) outputs,
and commonly form the third-phase command signals for direct-PWM output of brushless motors. Note
that if using the channel for direct-PWM control of a motor, the PFM outputs will not be seen on the same
channel.
For board-level Turbo PMAC2 controllers and 3U-format stack boards (Acc-1E and 2E), the Acc-8S
breakout board usually is the most effective way of bringing out the pulse-and-direction signals. These
signals are available also on the Acc-8A and Acc-8E analog breakout boards and the Acc-8F PWM
breakout boards (as the third-phase PWM).
The pulse-and-direction signals are available on the encoder connectors of the QMAC boxed controller
and of the UMAC Acc-24E2S, Acc-24E2A, and Acc-24E2 axis-interface boards. The outputs use the
same pins as the T, U, V, and W flag inputs for the channel; a jumper must be installed to enable the
outputs on these pins.
Signal Timing
The PULSEn and DIRn signals are driven from the internal PFMCLK signal, whose frequency is controlled
by I7m03 (see below). The width of the pulse is controlled by the PFMCLK frequency and I7m04 (see
below). The output on PULSEn can be high-true (high during pulse, low otherwise) or low-true, as
controlled by I7mn7; the default is high-true. The polarity of the DIRn signal is controlled by I7mn8.
PULSEn and DIRn signals can change only on the rising edge of PFMCLK. If DIRn changes on a pulse,
it will change simultaneously with the front end of PULSEn. Some stepper drives require a setup time on
the DIRn line before the rising edge of PULSEn; these systems can be accommodated by inverting the
PULSEn signal with I7mn7.
The DIRn signal is latched in this state at least until the front end of the next pulse. The PULSEn signal
stays true for the number of PFMCLK cycles set by I7m04. It then goes false and stays false for a
minimum of this same time. This guarantees that the pulse duty cycle never exceeds 50%; the pulse
signal can be inverted with I7mn7 without violating minimum pulse width specifications.
by I7m03 (see below). The width of the pulse is controlled by the PFMCLK frequency and I7m04 (see
below). The output on PULSEn can be high-true (high during pulse, low otherwise) or low-true, as
controlled by I7mn7; the default is high-true. The polarity of the DIRn signal is controlled by I7mn8.
PULSEn and DIRn signals can change only on the rising edge of PFMCLK. If DIRn changes on a pulse,
it will change simultaneously with the front end of PULSEn. Some stepper drives require a setup time on
the DIRn line before the rising edge of PULSEn; these systems can be accommodated by inverting the
PULSEn signal with I7mn7.
The DIRn signal is latched in this state at least until the front end of the next pulse. The PULSEn signal
stays true for the number of PFMCLK cycles set by I7m04. It then goes false and stays false for a
minimum of this same time. This guarantees that the pulse duty cycle never exceeds 50%; the pulse
signal can be inverted with I7mn7 without violating minimum pulse width specifications.