Delta Tau GEO BRICK LV User Manual
Turbo PMAC User Manual
Basic Motor Setup
81
Turbo PMAC Parameter Setup
Hardware Setup for PMAC2-Style ICs
PFM Clock Frequency: I7m03, I6803, MI903, MI907, MI993
An I-variable controls the frequency of addition of the command value into the accumulator by setting the
frequency of a clock signal called PFMCLK. One addition is performed during each PFMCLK cycle, so
the addition frequency is equal to the PFMCLK frequency. The pulse frequency for a given command
value is directly proportional to this addition frequency. While the default frequency is suitable for
almost all applications, those requiring very high or very low pulse frequencies may need to change this
clock frequency.
An I-variable controls the frequency of addition of the command value into the accumulator by setting the
frequency of a clock signal called PFMCLK. One addition is performed during each PFMCLK cycle, so
the addition frequency is equal to the PFMCLK frequency. The pulse frequency for a given command
value is directly proportional to this addition frequency. While the default frequency is suitable for
almost all applications, those requiring very high or very low pulse frequencies may need to change this
clock frequency.
This PFMCLK/addition frequency puts an upper limit on the pulse frequency that can be generated – with
an absolute limit of 1/4 of the PFMCLK/addition frequency. Depending on the worst-case frequency
distortion that can be tolerated at high speeds, most people will limit their maximum pulse frequency to
1/10 of the PFMCLK/addition frequency, therefore selecting a PFMCLK/addition frequency 10 to 20
times greater than their maximum desired pulse frequency.
an absolute limit of 1/4 of the PFMCLK/addition frequency. Depending on the worst-case frequency
distortion that can be tolerated at high speeds, most people will limit their maximum pulse frequency to
1/10 of the PFMCLK/addition frequency, therefore selecting a PFMCLK/addition frequency 10 to 20
times greater than their maximum desired pulse frequency.
The PFMCLK/addition frequency sets a lower limit on the pulse frequency as well – an absolute limit of
one eight-millionth of the addition frequency (without dithering). The default frequency of approximately
10 MHz can provide a useful range of about 1 Hz to 1 million Hz, and is suitable for a wide variety of
applications, especially with microstepping drives. For full or half step drives, the PFMCLK/addition
frequency probably will be set considerably lower – to the approximately 1.2 MHz or 600 kHz settings.
one eight-millionth of the addition frequency (without dithering). The default frequency of approximately
10 MHz can provide a useful range of about 1 Hz to 1 million Hz, and is suitable for a wide variety of
applications, especially with microstepping drives. For full or half step drives, the PFMCLK/addition
frequency probably will be set considerably lower – to the approximately 1.2 MHz or 600 kHz settings.
I7m03 controls the PFMCLK frequency for all of the axis-interface channels on Servo IC m; I6803 does
the same for the two supplementary channels on the handwheel port. On a MACRO Station, MI903,
MI907, and MI997 control this frequency. The input to the clock control circuitry is a 39.3216 MHz
signal; this can be divided by 1, 2, 4, 8, 16, 32, 64, or 128 to create the PFMCLK signal. Therefore, the
possible PFMCLK frequencies and the I-variable values that set them are:
the same for the two supplementary channels on the handwheel port. On a MACRO Station, MI903,
MI907, and MI997 control this frequency. The input to the clock control circuitry is a 39.3216 MHz
signal; this can be divided by 1, 2, 4, 8, 16, 32, 64, or 128 to create the PFMCLK signal. Therefore, the
possible PFMCLK frequencies and the I-variable values that set them are:
Divide by:
Divider N (1/2^N)
PFMCLK Freq
I-Variable Value*
1 0
39.3216
MHz
2240
2 1
19.6608
MHz
2249
4 2
9.8304
MHz
2258
8 3
4.9152
MHz
2267
16 4
2.4576
MHz
2276
32 5
1.2288
MHz
2285
64 6
611.44
kHz
2294
128 7
305.72
kHz
2303
*SCLK frequency = PFMCLK frequency; ADCCLK and DACCLK frequencies at default
The divider N is used in these I-variables to determine the frequency.
These variables also independently control the frequencies of the encoder sample clock SCLK, plus the
clocks for the serial D/A and A/D converters, DACCLK and ADCCLK, which are also divided down in
the same way from the same 39.3216 MHz signal. The SCLK frequency should be the same as the
PFMCLK frequency if the pulse train is fed into the encoder counters. The above table shows the value
of the I-variable for each possible frequency of the PFMCLCK, assuming the SCLK frequency is set
equal to the PFMCLK frequency, and the DACCLK and ADCCLK frequencies are left at their default
settings.
clocks for the serial D/A and A/D converters, DACCLK and ADCCLK, which are also divided down in
the same way from the same 39.3216 MHz signal. The SCLK frequency should be the same as the
PFMCLK frequency if the pulse train is fed into the encoder counters. The above table shows the value
of the I-variable for each possible frequency of the PFMCLCK, assuming the SCLK frequency is set
equal to the PFMCLK frequency, and the DACCLK and ADCCLK frequencies are left at their default
settings.