Lucent Technologies MN10285K User Manual
Timers
16-Bit Timer Setup Examples
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
100
Panasonic
Two potential types of errors are inherent with PWM output. First, because of the
circuit configuration, direction errors can occur. The output circuit is configured
with T flip-flops, so that even if one transition is missed, the 1s and 0s can
with T flip-flops, so that even if one transition is missed, the 1s and 0s can
reverse direction. Timers 4 and 5 contain an S-R flip-flop to prevent this type of
error. Second, if the duty cycle changes dynamically, which often happens in
error. Second, if the duty cycle changes dynamically, which often happens in
PWM output, the PWM waveform may skip a pulse (see the single buffering
section of figure 4-31 below). To prevent these misses, timers 4 and 5 provide a
section of figure 4-31 below). To prevent these misses, timers 4 and 5 provide a
double-buffer mode. In this mode, no matter what the timing of a TMnCB
change, the duty change does occur until the beginning of the next cycle, and no
change, the duty change does occur until the beginning of the next cycle, and no
signals are lost. Performance is assured even when the output switches from all
1s to all 0s (see the double buffering section of figure 4-31 below).
1s to all 0s (see the double buffering section of figure 4-31 below).
For this reason, you must always use double-buffer mode for PWM waveform
output. Use single-buffer mode only in applications that are unaffected by these
issues.
issues.
Figure 4-31 Single-Phase PWM Output Timing with Dynamic Duty Changes
(Timer 4)
0
1
2
3
4
0
0
1
2
3
4
0
1
2
3
4
0
1
2
3
B
A
B
A
B
B
A
3
1
3
1
3
1
3
1
TM4EN
Write to TM4CB
TM4CB
TM4BC
BOSC/4
CLRBC4
(1) Double buffering
TM4CB
TM4CBX
S4
R4
TM4OA
Interrupts
(2) Single buffering
TM4CB
S4
R4
TM4OA
Interrupts
A
B
A
B
B
A
No PWM or interrupt errors
Lost interrupt, causing a PWM output error