Lucent Technologies MN10285K User Manual

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6.

Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0. 

This enables TM4BC and the S-R flip-flop. This step ensures stable opera-
tion. If it is omitted, the binary counter may not count the first cycle. Do not 

change any other operating modes during this step.

7.

Set TM4NLD and TM4EN to 1. This starts the timer. Counting begins at the 

start of the next cycle.

Timer 4 can output a single-phase PWM signal at any duty. You must select up 

counting. Timer 4 does not operate in STOP mode, when B

OSC

 is off. If you use 

an external clock, it must be synchronized to B

OSC

.

In this procedure, you set the cycle (x’0001’ to x’FFFE’) in the TM4CA register 

and the duty in the TM4CB register. When the contents of TM4BC match those 
of the TM4CB register, the S-R flip-flop resets at the beginning of the next cycle. 

Please note the following:

■

When -1 

≤

 TM4CB 

<

 TM4CA, TM4OA output is low during the 0 to 

TM4CB + 1 cycles of the TM4CA + 1 cycle period and high during the 
remainder of the cycles.

■

When TM4CA 

≤

 TM4CB 

≤

 x’FFFE, TM4OA output is always low.

■

When TM4BC = x’FFFF’, TM4OA output is always high.

The circuitry is configured so that there are no waveform errors, even when the 
output is always high or always low. Counting begins after the TM4EN bit is set 

in the TM4MD register.