User ManualTable of ContentsChapter 1 Introduction101.1 Features111.2 Applications121.3 Installation Guide13Figure 1.1: Installation Flow Chart141.4 Software Overview151.5 Device Driver Programming Roadmap161.6 Accessories18Chapter 2 Installation202.1 Unpacking202.2 Driver Installation21Figure 2.1: Setup Screen of Advantech Automation Software22Figure 2.2: Different Options for Driver Setup222.3 Hardware Installation232.4 Device Setup & Configuration24Figure 2.3: The Device Manager Dialog Box24Figure 2.4: The Device Setting Dialog Box25Figure 2.5: Device Name Appearing on the List of Devices Box25Figure 2.6: The Test Utility Dialog Box26Chapter 3 Signal Connections283.1 Overview283.2 Switch and Jumper Settings28Figure 3.1: Card Connector, Jumper and Switch Locations283.2.1 Setting the BoardID Switch (SW1)29Board ID Setting (SW1)293.2.2 Channel Configuration, S/E or DIFF (SW2)30Summary of Switch SW2 Settings303.2.3 D/A Reference Voltage, int./ext. (JP11)30Summary of Jumper JP11 Settings303.2.4 Internal Voltage Reference, -10 V or -5 V (JP10)31Summary of Jumper JP10 Settings313.2.5 Timer Clock Selection (JP8)32Summary of Jumper JP8 Settings323.2.6 Ext. trigger and Counter Gate 0 Control (JP5)33Summary of Jumper Settings333.2.7 Digital Output, 20-pin or 37-pin Connector (JP1)33Summary of Jumper Settings343.2.8 Setting the Time to Reset Digital Outputs35JP21 Jumper Settings353.3 Signal Connections36Figure 3.2: I/O Connector Pin Assignments for the PCI-1718 Series363.3.1 I/O Connector Signal Description37I/O Connector Signal Descriptions373.3.2 Analog Input Connections38Figure 3.3: Analog Output Connections413.3.3 Digital Signal Connections423.4 Field Wiring Considerations43Chapter 4 Programming Guide464.1 Overview464.2 Programming with the Driver464.3 Register Programming.464.3.1 Software Trigger and Polling474.3.2 Pacer Trigger Mode with Interrupt494.3.3 Pacer Trigger Mode with Interrupt and FIFO534.4 Programming with LabVIEW and ActiveDAQ57Appendix A Specifications60A.1 Analog Input60A.2 Analog Output61A.3 Digital Input61A.4 Digital Output62A.5 Counter/Timer62A.6 General63Appendix B Block Diagrams66Appendix C Register Structure & Format68C.1 Overview68C.2 I/O Port Address Map68PCI-1718HDU/HGU Register Format (Part 1)69PCI-1718HDU/HGU Register Format (Part 2)70PCI-1718HDU/HGU Register Format (Part 3)71C.3 A/D Data and Channels - BASE+00H~01H72Register for A/D Data and Channels72C.4 Software A/D Trigger - BASE+00H72Register for Software A/D Trigger72C.5 A/D Range Control - BASE+01H73Register for A/D Range Control73C.6 MUX Scan Channel Control - BASE+02H75Register for MUX Scan Channel Control75C.7 MUX Scan Channel Status - BASE+02H76Register for MUX Scan Channel Status76C.8 Digital I/O Registers - BASE + 03/0BH76Register for Digital Output76Register for Digital Output77C.9 D/A Output - BASE+04/05H77Register for D/A Output77C.10 FIFO Interrupt Control - BASE+06H78Register for FIFO Interrupt Control78C.11 Clear Interrupt Request - BASE+08H79Register for Clear Interrupt Request79C.12 A/D Status - BASE+08H79Register for A/D Status79C.13 A/D Control - BASE+09H81Register for A/D Control81C.14 Timer/Counter Enable - BASE+0AH82Register for Timer/Counter Enable82C.15 Programmable Timer/Counter - BASE+0C~0FH82C.16 Clear FIFO Interrupt Request - BASE+14H83Register for Clear FIFO Interrupt Request83C.17 A/D Data and Channel from FIFO - BASE + 17/18H83Register for A/D Data and Channel from FIFO83C.18 FIFO Status - BASE+19H84Register for FIFO Status84C.19 FIFO Clear - BASE+19H84Register for FIFO Clear84C.20 Register Programming Flow Chart85C.20.1 Software Trigger Mode with Polling85C.20.2 Pacer Trigger Mode with Interrupt86C.20.3 Pacer Trigger Mode with Interrupt [FIFO Used]87Appendix D Calibration90D.1 VR Assignment91Figure D.1: PCI-1718 VR Assignment91D.2 A/D Calibration92D.3 D/A Calibration93Size: 1.52 MBPages: 94Language: EnglishOpen manual